Hold time latch with decreased precharge node voltage leakage

A dynamic logic hold time latch, comprising:

• a first phase circuit operable in a precharge phase and an evaluate phase, wherein the first phase circuit comprises:
• a precharge node to be precharged to a precharge voltage during the precharge phase of the first phase circuit and operable to be discharged during the evaluate phase of the first phase circuit;
• and
• an output for providing a signal in response to a state at the precharge node of the first phase circuit;
• and
• a second phase circuit operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the second phase circuit are out of phase with respect to the precharge phase and the evaluate phase of the first phase circuit, and wherein the second phase circuit comprises:
• a conditional discharge path connected to the precharge node of the second phase circuit and operable, during the evaluate phase of the second phase circuit and in response at least in part to the output of the first phase circuit, to conditionally couple the precharge node of the second phase circuit to a voltage different than the precharge voltage;
• wherein the conditional discharge path comprises at least one transistor of a first conductivity type and having a first threshold voltage;
• and
• wherein the first threshold voltage is lower than a threshold voltage of another transistor in the hold time latch having the first conductivity type;
• voltage maintaining circuitry, coupled to receive the output of the first phase circuit, for coupling the precharge voltage to the precharge node of the second phase circuit during the evaluate phase of the second phase circuit in response to the output of the first phase circuit providing a first value;
• wherein the voltage maintaining circuitry comprises at least one transistor of a second conductivity type, complementary to the first conductivity type, and having a second threshold voltage;
• and
• wherein the second threshold voltage is lower than a threshold voltage of another transistor in the hold time latch having the second conductivity type.

A dynamic logic hold time latch, comprising:

• a first phase circuit operable in a precharge phase and an evaluate phase, and comprising:
• a precharge node to be precharged to a precharge voltage during the precharge phase of the first phase circuit and operable to be discharged during the evaluate phase of the first phase circuit;
• and
• an output for providing a signal in response to a state at the precharge node of the first phase circuit;
• a second phase circuit operable in a precharge phase and an evaluate phase, wherein the precharge phase and the evaluate phase of the second phase circuit are out of phase with respect to the precharge phase and the evaluate phase of the first phase circuit, and wherein the second phase circuit comprises:
• a precharge node to be precharged to the precharge voltage during the precharge phase of the second phase circuit and operable to be discharged during the evaluate phase of the second phase circuit;
• a conditional discharge path connected to the precharge node of the second phase circuit and operable, during the evaluate phase of the second phase circuit and in response at least in part to the output of the first phase circuit, to conditionally couple the precharge node of the second phase circuit to a voltage different than the precharge voltage;
• and
• voltage maintaining circuitry, coupled to receive the output of the first phase circuit, for coupling the precharge voltage to the precharge node of the second phase circuit during at least a portion of the evaluate phase of the second phase circuit during instances wherein the conditional discharge path is not enabled.

A method of operating a dynamic logic hold time latch, comprising:

• operable in a precharge phase and an evaluate phase, and comprising:
• in a first phase circuit, precharging a precharge node to a precharge voltage during a precharge phase of the first phase circuit
• in a second phase circuit, precharging a precharge node to a precharge voltage during a precharge phase of the second phase circuit;
• in the first phase circuit, ending the precharge phase such that the precharge voltage may be discharged during an evaluate phase of the first phase circuit;
• in the second phase circuit, ending the precharge phase such that during an evaluate phase of the second phase circuit the precharge voltage at the precharge node of the second phase circuit may be discharged through a conditional discharge path, wherein the conditional discharge path is operable to conduct in response to an output from the first phase circuit and generated in response to the evaluate phase of the first phase circuit;
• and
• in response to the output of the first phase circuit, coupling the precharge voltage to the precharge node of the second phase circuit during at least a portion of the evaluate phase of the second phase circuit during instances wherein the conditional discharge path is not enabled.