US 2004/0104732 A1 · Semiconductor integrated circuit device

Abstract

An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, the selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the usual operation. Thereby, it is possible in a semiconductor integrated circuit comprising the analog and digital sections to eliminate adverse effect, even if the input/output pin for test corresponding to the test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, from the analog circuit due to the noise which is generated in the digital section and is then transferred to the analog circuit through the signal path up to the analog input/output pin connected to the test circuit from this test circuit of the digital section.

Claims10

Dependent claims

A semiconductor integrated circuit of the structure that analog circuits and digital circuits are formed on one semiconductor substrate and an external terminal of said analog circuits is used in common as an external terminal of said digital circuits,

wherein selection switches are respectively provided in the course of the wiring connecting between said external terminal and said analog circuit and the wiring connecting between said external terminal and said digital circuits, and
wherein voltage fixing means is connected to the wiring connecting between said selection switches and said digital circuit for fixing the relevant wiring to the predetermined voltage under the condition that the relevant selection switch is in the shut-off condition.

A semiconductor integrated circuit for signal process comprising:

an oscillation control circuit for generating a control voltage of a first oscillation circuit for generating a first oscillation signal and a second oscillation circuit for generating a second oscillation signal;
receiving analog circuits including an amplifying circuit for amplifying a receiving signal, a first mixer circuit for combining the amplified signal and said first oscillation signal and converting the frequency thereof and a demodulation circuit for demodulating the signal frequency-converted in said first mixer circuit;
analog circuits including a modulation circuit for modulating a transmitting signal and a circuit for combining the modulated signal and said second oscillation signal;
a control digital circuit for controlling said receiving analog circuits and transmitting analog circuits;
and
a test circuit for outputting a signal from said control digital circuit to the external side;
wherein, at least an external terminal for inputting or outputting an analog input signal to said transmitting analog circuits or an analog output signal from said transmitting analog circuits is used in common as an external terminal for outputting a signal from said test circuit and selection switches are respectively provided in the course of the wiring connecting between said external terminal and said analog circuits and the wiring connecting between said external terminal and said digital circuits, and
wherein voltage fixing means is connected to a side nearer to said digital circuits than said selection switch of the wiring connecting between said external terminal and said digital circuits for fixing the relevant wiring to the predetermined voltage under the condition that the relevant selection switch is in the shut-off condition.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device

Life of this patent

Semiconductor integrated circuit device

Life of this patent

Abstract

Claims10