Plating tail design for IC packages
AssigneeInternational Business Machines Corporation
InventorsMark J. Kuzawinski, Edward M. Wolf
Life of this patent
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Abstract
A plating tail connected to a signal trace for use during an electroplating operation is fabricated such that it has a substantially different impedance from the signal trace at a characteristic frequency in use, so that adverse reflections during operation are reduced below a threshold of significance.
Claims18
A substrate for supporting and connecting a set of at least one ICs comprises a set of signal traces connected to said set of ICs, at least one of said set of signal traces having a trace characteristic impedance at an operating frequency and a plating tail connected thereto, in which said plating tail has a tail characteristic impedance at said operating frequency that is substantially different from said trace characteristic impedance, whereby reflections from said plating tail during operation are reduced below a reflection threshold.
A substrate for supporting and connecting a set of at least one ICs comprises a set of signal traces connected to said set of ICs and disposed on a first surface of said substrate, at least two of said set of signal traces having a trace characteristic impedance at an operating frequency and a vertical conductive via connected thereto and extending to a second surface of said substrate opposite said first surface, said second surface being an insulating surface in which said at least two vias are grouped in at least one group on said second surface containing no signal traces, whereby reflections from said plating tail during operation are reduced below a reflection threshold.
A method for fabricating a substrate for supporting and connecting a set of at least one ICs comprising the steps of forming a set of signal traces for connection to said set of ICs, said set of signal traces being disposed on a first surface of said substrate, and at least one of said set of signal traces having a trace characteristic impedance at an operating frequency;
- forming a vertical conductive via connected to said set of signal traces and extending to a second insulating surface of said substrate opposite said first surface;
- forming at least one plating tail connected to said at least one conductive via;
- plating said set of signal traces;
- and
- removing said at least one plating tail, whereby reflections from said conductive via during operation are reduced below a reflection threshold.
A method for fabricating a substrate for supporting and connecting a set of at least one ICs comprising the steps of forming a set of signal traces for connection to said set of ICs, said set of signal traces being disposed on a first surface of said substrate, and at least one of said set of signal traces having a trace characteristic impedance at an operating frequency;
- forming a vertical conductive via connected to said set of signal traces and extending to a second insulating surface of said substrate opposite said first surface;
- forming at least one plating tail, connected to said at least one conductive via and having a tail characteristic impedance substantially different from said trace characteristic impedance;
- and
- plating said set of signal traces.
Dependencies are inferred from the claim text.