US 2004/0104457 A1Published application

High density chip scale leadframe package and method of manufacturing the package

AssigneeUnited Test and Assembly Test Center Ltd.

InventorsHien Boon Tan, Anthony Yi Sheng Sun

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Abstract

An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Claims26

Dependent claims

An integrated circuit package, comprising:

a) a die pad having a first face and a second face opposite to said first face;
b) a plurality of inner leads each having a first face and a second face opposite to said first face, and a plurality of sides between said first face and said second face, wherein said plurality of inner leads is disposed substantially co-planar with and substantially around said die pad;
c) a plurality of outer leads each having a first face and a second face opposite to said first face, and a plurality of sides between said first face and said second face, wherein said plurality of outer leads is disposed substantially co-planar with and substantially around said plurality of inner leads and said die pad, such that said sides of each of said plurality of outer leads are substantially offset from said sides of each of said plurality of inner leads;
d) a first adhesive layer disposed on said first face of said die pad;
e) a second adhesive layer disposed on said first face of said plurality of inner leads;
f) an integrated circuit chip having a first face and a second face opposite to said first face,
wherein said second face of said integrated circuit chip is coupled to said first face of said die pad through said first adhesive layer, and
wherein said second face of said integrated circuit chip is further coupled to said first face of said plurality of inner leads through said second adhesive layer;
g) a first plurality of wires linking said plurality of inner leads to said integrated circuit chip, each of said first plurality of wires comprising:
a first end electrically conductively joined to said first face of one of said plurality of inner leads, and
a second end electrically conductively joined to said first face of said integrated circuit chip;
and
h) a second plurality of wires linking said plurality of outer leads to said integrated circuit chip, each of said second plurality of wires comprising:
a first end electrically conductively joined to said first face of one of said plurality of outer leads, and
a second end electrically conductively joined to said first face of said integrated circuit chip.

12 more elements

An integrated circuit package, comprising:

a) a die pad having a first face and a second face opposite to said first face;
b) a plurality of inner leads each having a first face and a second face opposite to said first face, and a plurality of sides between said first face and said second face, wherein said plurality of inner leads is disposed substantially co-planar with and substantially around said die pad;
c) a plurality of outer leads each having a first face and a second face opposite to said first face, and a plurality of sides between said first face and said second face, wherein said plurality of outer leads is disposed substantially co-planar with and substantially around said plurality of inner leads and said die pad, such that said sides of each of said plurality of outer leads are substantially offset from said sides of each of said plurality of inner leads;
d) a first adhesive layer disposed on said first face of said die pad;
e) a second adhesive layer disposed on said first face of said plurality of inner leads;
f) a first integrated circuit chip having a first face and a second face opposite to said first face,
wherein said section face of said first integrated circuit chip is coupled to said first face of said die pad through said first adhesive layer, and
wherein said second face of said first integrated circuit chip is further coupled to said first face of said plurality of inner leads through said second adhesive layer;
g) a third adhesive layer disposed on said first face of said first integrated circuit chip;
h) a second integrated circuit chip having a first face and a second face opposite to said first face,
wherein said second face of said second integrated circuit chip is coupled to said first face of said first integrated circuit chip through said third adhesive layer;
i) a first plurality of wires linking said plurality of inner leads to said first integrated circuit chip, each of said first plurality of wires comprising:
a first end electrically conductively joined to said first face of one of said plurality of inner leads, and
a second end electrically conductively joined to said first face of said first integrated circuit chip;
and
j) a second plurality of wires linking said plurality of outer leads to said second integrated circuit chip, each of said second plurality of wires comprising:
a first end electrically conductively joined to said first face of one of said plurality of outer leads, and
a second end electrically conductively joined to said first face of said second integrated circuit chip.

15 more elements

A method of assembling an integrated circuit package, comprising:

a) providing:
a die pad having a first face and a second face opposite to said first face,
a plurality of inner leads each having a first face and a second face opposite to said first face, and a plurality of sides between said first face and said second face,
a plurality of outer leads each having a first face and a second face opposite to said first face, and a plurality of sides between said first face and said second face,
an integrated circuit chip having a first face and a second face opposite to said first face, and
a conductive element having a first face and a second face opposite to said first face;
b) disposing said inner leads substantially co-planar with and substantially around said die pad;
c) disposing said outer leads substantially co-planar with and substantially around said inner leads and said die pad, such that said plurality of sides of said plurality of outer leads is offset from said plurality of sides of said plurality of inner leads;
d) coupling said second face of said conductive element to said first face of said die pad through a first adhesive layer;
e) further coupling said second face of said conductive element to said first faces of said plurality of inner leads through a second adhesive layer;
f) coupling said second face of said integrated circuit chip to said first face of said conductive element through a third adhesive layer;
g) electrically conductively linking each of said plurality of inner leads to said first face of said integrated circuit chip;
h) electrically conductively linking each of said plurality of outer leads to said first face of said integrated circuit chip;
i) electrically conductively linking said first face of said integrated circuit chip to said conductive element;
and
j) electrically conductively linking said conductive element to said die pad.

13 more elements

A method of assembling an integrated circuit package, comprising:

a) providing:
a leadframe having a first face and a second face opposite to said first face, wherein said leadframe comprises:
an outer frame portion,
a die pad portion substantially centrally disposed within said outer frame portion,
a plurality of inner lead portions extending substantially radially outward from said die pad portion, each of said plurality of inner leads comprising an inner portion, a central portion and an outer portion,
a plurality of outer lead portions extending substantially radially inward from said outer frame portion, and
a plurality of tie bars connecting said die pad portion to said outer frame portion, each of said plurality of tie bars comprising an inner portion and an outer portion,
an integrated circuit chip having a first face and a second face opposite to said first face,
a first plurality of wires each having a first end and a second end, and
a second plurality of wires each having a first end and a second end;
b) disposing an adhesive layer on said first face of said leadframe, whereby said first adhesive layer covers said die pad portion, said inner portion and said central portion of said plurality of inner lead portions, and said inner portion of said plurality of tie bars, and whereby said outer portion of said plurality of inner lead portions remains free of adhesive;
c) severing said outer and central portions of said plurality of inner lead portions from said inner portions of said plurality of inner lead portions and from said die pad portion;
d) mounting said integrated circuit chip on said leadframe, whereby said second face of said integrated circuit chip is connected to said first face of said die pad portion through said adhesive layer, and whereby said second face of said integrated circuit chip is further connected to said first faces of said plurality of inner lead portions through said adhesive layer;
e) electrically conductively joining said first end of each of said first plurality of wires to said first face of said outer portion of one of said plurality of inner lead portions;
f) electrically conductively joining said second end of each of said first plurality of wires to said first face of said integrated circuit chip;
g) electrically conductively joining said first end of each of said second plurality of wires to said first face of one of said plurality of outer leads;
and
h) electrically conductively joining said second end of said second plurality of wires to said first face of said integrated circuit chip.

15 more elements

A method of assembling an integrated circuit package, comprising:

a) providing:
a leadframe having a first face and a second face opposite to said first face, wherein said leadframe comprises:
an outer frame portion,
a die pad portion substantially centrally disposed within said outer frame portion,
a plurality of tie bars connecting said die pad portion to said outer frame portion, and
a plurality of protuberances extending substantially radially inward from said outer frame portion, each of said plurality of protuberances comprising an inner lead portion, and
outer lead portion, and a post portion connecting said inner lead portion from said outer lead portion,
an integrated circuit chip having a first face and a second face opposite to said first face,
a first plurality of wires each having a first end and a second end, and
a second plurality of wires each having a first end and a second end;
b) disposing an adhesive layer on said first face of said leadframe, whereby said adhesive layer covers said die pad portion, and part of said inner lead portion of each of said plurality of protuberances, wherein part of each of said inner lead portions remains free of adhesive;
c) severing said outer lead portion from said inner lead portion by cutting said post portion;
d) mounting said integrated circuit chip on said leadframe, whereby said second face of said integrated circuit chip is connected to said first face of said die pad portion through said adhesive layer, and whereby said second face of said integrated circuit is further connected to said inner lead portions through said adhesive layer;
e) electrically conductively joining said first end of said first plurality of wires to said first face of one of said plurality of inner lead portions;
f) electrically conductively joining said second end of each of said first plurality of wires to said first face of said integrated circuit chip;
g) electrically conductively joining said first end of each of said second plurality of wires to said first face of one of said outer lead portions, and
h) electrically conductively joining said second end of said second plurality of wires to said first face of said integrated circuit chip.

14 more elements

Dependencies are inferred from the claim text.