Methods and apparatus for reducing parasitic inductance using inter-digitated bond, wires

A microelectronic component with reduced parasitic inductance, said component comprising:

• a first semiconductor device coupled to a lead frame;
• a first set of bond wires connected to said first semiconductor device for providing current flow into said semiconductor device;
• a second set of bond wires connected to said first semiconductor device for providing current flow out of said semiconductor device;
• a second semiconductor device coupled to the lead frame adjacent to said semiconductor device;
• at least a portion of said first set of bond wires arranged to pass over at least a portion of said second semiconductor device;
• and
• a third set of bond wires connecting said second semiconductor device to a fixed potential;
• said at least portion of said first set of bond wires and at least a portion of said third set of bond wires arranged in proximity to each other and configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between said first and third set of bond wires.

A microelectronic component with reduced parasitic inductance, said component comprising:

• a first semiconductor device coupled to a lead frame;
• a first set of bond wires connected to said first semiconductor device;
• a second set of bond wires connected to said first semiconductor device;
• a second semiconductor device coupled to the lead frame adjacent to said first semiconductor device;
• a second lead frame placed over said second semiconductor device;
• said first set of bond wires being attached to said second lead frame;
• a third set of bond wires connecting said second semiconductor device to a fixed potential;
• said second lead frame having longitudinal cutouts, and
• said third set of bond wires being arranged along said longitudinal cutouts configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the third set of bond wires and said second lead frame.

A microelectronic component with reduced parasitic inductance, said component comprising:

• an elongated semiconductor device, having two long and two short sides, coupled to a substrate;
• a first set of bond wires connected along at least one of said two long sides of said semiconductor device for providing current flow into said semiconductor device;
• a second set of bond wires that are in a current loop with said first set of bond wires and are connected to said semiconductor device for providing current flow out of said semiconductor device;
• said first and second set of bond wires configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between said first and second set of bond wires.