Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers
AssigneeAdvanced Micro Devices, Inc.
InventorsThomas Feudel, Manfred Horstmann, Karsten Wieczorek, Stephan Kruegel
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Abstract
High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.
Claims31
A method of forming a field effect transistor, the method comprising:
- forming a doped high-k dielectric layer over a substrate including a gate electrode formed above an active region and separated therefrom by a gate insulation layer;
- heat treating said substrate to diffuse dopants from said high-k dielectric layer into said active region to form extension regions;
- patterning said high-k dielectric layer to form sidewall spacers at sidewalls of said gate electrode;
- and
- performing an ion implantation process using said sidewall spacers as an implantation mask to form source and drain regions of said field effect transistor.
A method of forming a field effect transistor, the method comprising:
- performing an ion implantation process to form source and drain regions in an active region formed in a substrate, said substrate including a gate electrode formed over said active region and separated therefrom by a gate insulation layer, said gate electrode having sidewall spacers formed on sidewalls thereof;
- removing said sidewall spacers;
- forming a doped high-k dielectric layer over said substrate;
- annealing said substrate to introduce dopants from said doped high-k layer into said active region;
- and
- patterning said high-k dielectric layer to form high-k sidewall spacers at sidewalls of said gate electrode.
A method of forming a shallow doped semiconductor region below a dielectric region, the method comprising:
- forming a dielectric layer over said semiconductor region, said dielectric layer comprising an oxide of at least one of tantalum, zirconium, hafnium, lanthanum, yttrium and strontium;
- introducing a dopant material into said dielectric layer;
- annealing the substrate to diffuse dopant material from said dielectric layer into said semiconductor region;
- and
- patterning said dielectric layer to form a dielectric region above said doped semiconductor region;
- wherein charge carrier accumulation below said dielectric region is enhanced in the presence of an external electric field due to said dielectric region.
A field effect transistor, comprising:
- a gate electrode formed above an active semiconductor region and separated therefrom by a gate insulation layer, said active semiconductor region having a dopant concentration;
- and
- doped high-k dielectric spacer elements formed on sidewalls of said gate electrode and over a portion of said active semiconductor region;
- wherein a dopant concentration at a part of an interface between said high-k dielectric spacer elements and said active semiconductor region is equal or higher than said dopant concentration of said active semiconductor region.
Dependencies are inferred from the claim text.