Back to results
US 2004/0104435 A1Published application
Semiconductor device and method of fabricating the same
AssigneeSemiconductor Energy Laboratory Co., Ltd., a Japan corporation
InventorsHisashi Ohtani, Etsuko Fujimoto
Life of this patent
Estimating the term…
Abstract
There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
Claims12
A semiconductor device comprising:
- a gate electrode;
- a gate insulator film wider than said gate electrode;
- an active layer;
- a pair of n- or p-type doped regions formed in said active layer;
- a pair of silicide layers self-aligned to said gate insulator film, said silicide layers consisting mainly of a metal material and silicon;
- a first metallization layer in intimate contact with said silicide layers, said first metallization layer being made of said metal material;
- and
- a top layer of interconnect metal formed over said gate electrode and connected with said first metallization layer via at least one contact.
5 more elements
A semiconductor device comprising:
- a gate electrode formed in a layer;
- a gate insulator film wider than said gate electrode;
- an active layer;
- a pair of n- or p-type doped regions formed in said active layer;
- a pair of silicide layers self-aligned to said gate insulator film, said silicide layers consisting mainly of a metal material and silicon;
- a first metallization layer in intimate contact with said silicide layers, said first metallization layer being made of said metal material;
- a second metallization layer that is in intimate contact with said first metallization layer, similar in geometry to said first metallization layer, and made of a material having a smaller resistivity than the material of said first metallization layer;
- and
- conductive interconnects formed in the same layer as said gate electrode and connected with said first metallization layer via at least one contact.
6 more elements
A method of fabricating a semiconductor device, comprising the steps of:
- forming a gate insulator layer and a gate electrode on an active layer;
- etching said gate insulator layer to form a gate insulator film wider than said gate electrode;
- forming a first metallization layer out of a material in intimate contact with said active layer;
- reacting said active layer with said first metallization layer to form silicide layers self-aligned to said gate insulator film;
- and
- selectively etching said first metallization layer.
3 more elements
Dependencies are inferred from the claim text.