Graded composition gate insulators to reduce tunneling barriers in flash memory devices

A flash memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region;
• a first gate opposing the channel;
• a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height for charge injection;
• and
• a second gate separated from the first gate insulator by a second gate insulator.

A flash memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region;
• a floating gate opposing the channel;
• a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap and large electron affinity, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiOx with 1 ( ×( 2) layer in combination with a SiO2 layer to form the graded composition gate insulator;
• and
• a control gate separated from the floating gate insulator by a second gate insulator.

A flash memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region;
• a floating gate opposing the channel;
• a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap and large electron affinity, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide (SixCyOz) layer in combination with a SiO2 layer to form the graded composition gate insulator;
• and
• a control gate separated from the floating gate insulator by a second gate insulator.

A flash memory cell, comprising:

• a first source/drain region and a second source/drain region separated by a channel region;
• a floating gate opposing the channel;
• a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of 3.0 to 3.2 eV and a large electron affinity of 3.5 to 3.7 eV;
• and
• a control gate separated from the floating gate insulator by a second gate insulator.

A method of forming a flash memory cell, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region;
• forming a first gate opposing the channel;
• forming a first gate insulator separating the first gate from the channel, wherein forming the gate insulator includes forming a graded composition gate insulator such that the graded composition gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV;
• and
• forming a second gate separated from the first gate by a second gate insulator.

A method for forming a flash memory cell, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region;
• forming a first gate opposing the channel;
• forming a first gate insulator having two layers separating the first gate from the channel, wherein forming the first gate insulator includes forming a first layer and forming a second layer to have a similar dielectric constant in order to keep the electric fields comparable in each layer, and wherein forming the first gate insulator includes forming a first gate insulator to have a low electron barrier height for charge injection;
• and
• forming a second gate separated from the first gate by a second gate insulator.

A method of forming a flash memory cell, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region;
• forming a floating gate opposing the channel;
• forming a first gate insulator separating the floating gate from the channel, wherein the first gate insulator includes forming a graded composition gate insulator having a low band gap and large electron affinity, and wherein forming the graded composition gate insulator includes forming a dielectric material having a silicon suboxide (SiOx with 1 ( ×( 2) layer in combination with a SiO2 layer to form the graded composition gate insulator;
• and
• forming a control gate separated from the floating gate insulator by a second gate insulator.

A method for forming a flash memory cell, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region;
• forming a floating gate opposing the channel;
• forming a first gate insulator separating the floating gate from the channel, wherein forming the gate insulator includes forming a graded composition gate insulator having a low band gap and large electron affinity, and wherein forming the graded composition gate insulator includes forming a dielectric material having a silicon oxycarbide (SixCyOz) layer in combination with a SiO2 layer to form the graded composition gate insulator;
• and
• forming a control gate separated from the floating gate insulator by a second gate insulator.