Transistor array and semiconductor memory configuration fabricated with the transistor array
AssigneeInfineon Technologies AG
InventorsBernhard Kowalski, Andreas Felber, Valentin Rosskopf, Till Schlosser, Jurgen Lindolf
Life of this patent
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Abstract
A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.
Claims12
A transistor array, comprising:
- vertical FET transistors each formed of vertical and laterally parallel sections of active webs of semiconductor formed into a depth of a substrate;
- said vertical FET transistors having a channel region surrounded by gate strips, forming a gate electrode and running along said sections of active webs, and forming word lines for a memory cell array of semiconductor memory cells assigned to the transistor array;
- word line contacts electrically connecting at least some of said word lines to metal tracks of a metal plane superimposed on the transistor array;
- an insulation in a deep trench, passing into the depth of said active web, insulating said word line contacts from other elements, the deep trenches being formed with a substantially identical structure as deep trenches otherwise forming storage capacitors in the memory cell array, except for a buried strap connecting said active web in the memory cell array to polysilicon in the depth of the substrate and that is omitted in the deep trenches of the word line contacts.
A transistor array formed together with a memory cell array of semiconductor memory cells in a common first semiconductor well of a first conduction type in a substrate, the transistor array comprising:
- vertical FET transistors each formed of vertical and laterally parallel sections of active webs of semiconductor formed into a depth of a substrate;
- said vertical FET transistors having a channel region surrounded by gate strips, forming a gate electrode and running along said sections of active webs, and forming word lines for the memory cell array of semiconductor memory cells formed in the common well and assigned to the transistor array;
- word line contacts electrically connecting at least some of said word lines to metal tracks of a metal plane superimposed on the transistor array;
- all of said word lines leading into a second semiconductor well, separate and insulated from the first semiconductor well and having the same conduction type, and said word line contacts connecting said word lines to the metal tracks of the metal plane in the second semiconductor well.
Dependencies are inferred from the claim text.