CMOS imager with selectively silicided gate

( A method of forming a CMOS imager, comprising the steps of:

• forming an insulating layer over a semiconductor substrate having a photo-collection region;
• forming at least one transistor gate over a portion of said insulating layer;
• forming an opaque conductive layer over said photocollection region, said at least one transistor gate and said insulating layer;
• and
• selectively removing said opaque conductive layer from said insulating layer and said photocollection region.

A method of forming a CMOS imager, comprising the steps of:

• forming an insulating layer over a semiconductor substrate having a doped photocollection region;
• depositing a doped polysilicon layer over said insulating layer;
• depositing a photocollection insulator over said photocollection region;
• forming an opaque conductive layer over said doped polysilicon layer;
• and
• patterning said imager to form at least one gate stack having said opaque conductive layer over said gate stack.

(P A CMOS imager having improved transistor speed comprising:

• a substrate doped to a first conductivity type;
• an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed;
• and
• signal processing circuitry on said substrate, wherein said circuitry is connected to said array.

(I A processing system comprising:

• (i) a processor;
• and
• (ii) a CMOS imaging device coupled to said processor and including:
• a substrate doped to a first conductivity type;
• an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed;
• and
• signal processing circuitry on said substrate, wherein said circuitry is connected to said array.

1 A CMOS imager having improved transistor speed comprising:

• a substrate doped to a first conductivity type;
• an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor;
• and
• signal processing circuitry on said substrate, wherein said circuitry is connected to said array, wherein said photogate is void of said deposited opaque conductive layer.

9A processing system comprising:

• (i) a processor;
• and
• (ii) a CMOS imaging device coupled to said processor and including:
• a substrate doped to a first conductivity type;
• an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor;
• and
• signal processing circuitry on said substrate, wherein said circuitry is connected to said array, wherein said photogate is void of said deposited opaque conductive layer.