Method for producing a gate for a cmos transistor structure having a channel of reduced length

Process for making a gate (30, 49) for a CMOS transistor structure for which the gate length is shorter at the bottom than at the top, made from a stack realized on a face in a semi-conducting material of a substrate (20, 40), said stack comprising a gate isolation layer (21, 41), a gate material layer (22, 51, 52) and a gate mask (23, 42) in sequence, the process comprising the following steps:

• a) anisotropic etching of the top part of the gate material layer not masked by the gate mask (23, 42), this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit (24, 44) composed of etching products on the etching sides resulting from the anisotropic etching,
• c) etching of the bottom part of the gate material layer (21, 41) as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make to the gate (30, 49) a length shorter at the bottom than at the top,
• characterised in that there is a step b) between steps a) and c), for the treatment of the deposit (24, 44) composed of etching products, to make a protection layer (27, 46) reinforced against etching in step c).