Novel CMOS device

A semiconductor device comprising:

• at least one NMOS device;
• at least one PMOS device adjacent the at least one NMOS device;
• a first stress layer overlying the at least one PMOS device;
• the first stress layer having a first stress characteristic;
• and
• a second stress layer overlying the at least one NMOS device;
• the second stress layer having a second stress characteristic;
• whereby the first stress characteristic is tensile and the second stress characteristic is tensile;
• or the first stress characteristic is compressive and the second stress characteristic.

A semiconductor device comprising:

• at least one NMOS device;
• at least one PMOS device adjacent the at least one NMOS device;
• a first stress layer overlying the at least one PMOS device;
• the first stress layer having a first stress characteristic;
• and
• a second stress layer overlying the at least one NMOS device;
• the second stress layer having a second stress characteristic;
• whereby:
• (1) the first stress characteristic is tensile and the second stress characteristic is tensile, or
• the first stress characteristic is compressive and the second stress characteristic;
• and
• (2) the first stress layer is a rapid thermal CVD layer and the second stress layer is a rapid thermal CVD layer;
• or
• the first stress layer is a PECVD layer and the second stress layer is a rapid thermal CVD layer.

A method for improving the mobility of holes and electrons within a structure, comprising the steps of:

• providing a structure having at least an adjacent NMOS device and PMOS device;
• forming a first stress layer over the PMOS device;
• and
• forming a second stress layer over the NMOS device;
• whereby the mobility of holes and electrons within the structure is improved and wherein:
• the first stress layer is a tensile-stress layer and the second stress layer is a tensile-stress layer;
• or
• the first stress layer is a compression-stress layer and the second stress layer is a tensile-stress layer.