US 2004/0104401 A1 · METHOD OF FABRICATING THIN FILM TRANSISTOR ARRAY

Abstract

A method of fabricating a thin film transistor array is provided. A first patterned conductive layer that distributes over an area range exceeding the designated display region is formed over a substrate. A first dielectric layer is formed over the substrate, wherein the first dielectric layer has the thickness getting smaller toward the edge, so that the first patterned conductive layer outside the designated display region is exposed. A second patterned conductive layer is formed over the first dielectric layer. The second patterned conductive layer and the exposed first patterned conductive layer are electrically connected. A second dielectric layer having a plurality of contact openings therein is formed over the substrate. A plurality of pixel electrodes is formed over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings. Finally, various layers outside the designated display regions are removed.

Claims29

Dependent claims

A method of fabricating a thin film transistor array on a substrate having at least one designated display region, the method comprising the steps of:

forming a first patterned conductive layer over the substrate, wherein the first patterned conductive layer distributes over an area range that exceeds the designated display region;
forming a first dielectric layer over the substrate such that the first patterned conductive layer outside the designated display region is exposed;
forming a second patterned conductive layer over the first dielectric layer, wherein the second patterned conductive layer and the exposed first patterned conductive layer are electrically connected;
forming a second dielectric layer over the substrate, wherein the second dielectric layer has a plurality of contact openings;
forming a plurality of pixel electrode over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings;
and
removing the second dielectric layer, the second patterned conductive layer, the first dielectric layer and the first patterned conductive layer outside the designated display region.

4 more elements

A method of preventing damages due to electrostatic discharge applicable to a thin film transistor array having at least one designated display region, wherein the thin film transistor array at least includes a first patterned conductive layer distributed in an area range that exceeds the designated display region and that the first patterned conductive layer further includes a plurality of gates and a plurality of gate connected scan lines, a second patterned conductive layer over the first patterned conductive layer and that the second patterned conductive layer includes a plurality of source/drain terminals and a plurality of source/drain connected data lines, a first dielectric layer between the first patterned conductive layer and the second patterned conductive layer, a second dielectric layer over the second patterned conductive layer, and a pixel electrode over the second dielectric layer that connects electrically with one of the source/drain terminals, the method comprising the steps of:

forming the first dielectric layer such that the gates and the scan lines inside the designated display region are covered while the first patterned conductive layer outside the designated display region is exposed;
and
forming the second patterned conductive layer over the first patterned conductive layer such that the second patterned conductive layer and the exposed first patterned conductive layer are electrically connected.

Dependencies are inferred from the claim text.

Method of fabricating thin film transistor array

Life of this patent

Method of fabricating thin film transistor array

Life of this patent

Abstract

Claims29