Padless structure design for easy identification of bridging defects in lines by passive voltage contrast
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsZhigang Song, Shailesh Redkar, Chong Khiam Oh
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Abstract
A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.
Claims25
A test structure to locate bridging defects in a conductive layer of an integrated circuit device, said test structure comprising:
- a line comprising a conductive layer overlying a substrate wherein said line is coupled to ground;
- and
- a plurality of rectangles comprising said conductive layer wherein said rectangles are not connected to said line or to other said rectangles, wherein near edges of said rectangles and of said line are parallel, and wherein said rectangles are floating.
A method to locate bridging defects in a conductive layer of an integrated circuit device, said method comprising:
- providing a conductive layer overlying a substrate;
- patterning said conductive layer to form lines and to form a test structure wherein said test structure comprises:
- a line comprising said conductive layer overlying said substrate wherein said line is coupled to ground;
- and
- a plurality of rectangles comprising said conductive layer wherein said rectangles are not connected to said line or to other said rectangles, wherein near edges of said rectangles and of said line are parallel, wherein said near edges are spaced by a constant value, and wherein said rectangles are floating;
- exposing said test structure to an electron beam;
- and
- capturing emitted secondary electrons from said test structure to locate said briding defects by passive voltage contrast.
A method to measure critical dimensions in a conductive layer of an integrated circuit device, said method comprising:
- providing a conductive layer overlying a substrate;
- patterning said conductive layer to form lines and to form a test structure wherein said test structure comprises:
- a line comprising said conductive layer overlying said substrate wherein said line is coupled to ground;
- and
- a plurality of rectangles comprising said conductive layer wherein said rectangles are not connected to said line or to other said rectangles, wherein near edges of said rectangles and of said line are parallel, wherein said near edges are spaced by non-constant values, and wherein said rectangles are floating;
- exposing said test structure to an electron beam;
- capturing emitted secondary electrons from said test structure to locate short in said test structure by passive voltage contrast;
- and
- determining critical dimension as smallest said space without said short.
Dependencies are inferred from the claim text.