Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction

A processing unit for a data processing system having a global promotion facility and a plurality of processing units coupled by an interconnect, said processing unit comprising:

• an instruction sequencing unit;
• an execution unit coupled to the instruction sequencing unit, wherein said execution unit, responsive to a single acquisition instruction specifying a plurality of promotion bit fields within said global promotion facility, causes the processing unit to issue an access request to access to concurrently acquire all of said plurality of promotion bit fields exclusive of at least one other processing unit among said plurality of processing units;
• and
• a register including a register bit field indicating success or failure of said acquisition instruction, wherein said register bit field indicates success of said acquisition instruction if all of said plurality of promotion bit fields were concurrently acquired by said processing unit and indicates failure of said acquisition instruction if fewer than all of said plurality of promotion bit fields were acquired by said processing unit.

A data processing system, comprising:

• a global promotion facility containing a promotion bit field;
• an interconnect;
• a plurality of processing units coupled to said global promotion facility and to the interconnect, wherein said plurality of processing units includes a second processing unit and a first processing unit, said first processing unit comprising:
• an instruction sequencing unit;
• an execution unit coupled to the instruction sequencing unit, wherein said execution unit, responsive to a single acquisition instruction specifying a plurality of promotion bit fields within said global promotion facility, causes the first processing unit to issue an access request to concurrently acquire all of said plurality of promotion bit fields exclusive of at said second processing unit;
• and
• a register including a register bit field indicating success or failure of said acquisition instruction, wherein said register bit field indicates success of said acquisition instruction if all of said plurality of promotion bit fields were concurrently acquired by said first processing unit and indicates failure of said acquisition instruction if fewer than all of said plurality of promotion bit fields were acquired by said first processing unit.