US 2004/0073755 A1 · Broadcast invalidate scheme

Abstract

A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster. All processors within the cluster invalidate a local copy of the shared data if it exists and once the master processor receives acknowledgements from all processors in the cluster, the master processor sends an invalidate acknowledgment message to the processor that originally requested the exclusive rights to the shared data. The cache coherency is scalable and may be implemented using the hybrid point-to-point/broadcast scheme or a conventional point-to-point only directory-based invalidate scheme.

Claims20

Dependent claims

A method for managing distribution of messages for changing the state of shared data in a computer system having a main memory, a memory management system, a plurality of processors, each processor having an associated cache, and employing a directory-based cache coherency comprising the method of:

grouping the plurality of processors into a plurality of clusters;
tracking copies of shared data sent to processors in the clusters;
receiving an exclusive request from a processor requesting permission to modify a shared copy of the data;
generating invalidate messages requesting that other processors sharing the same data invalidate that data;
sending the invalidate messages only to clusters actually containing processors that have a shared copy of the data in the associated cache;
and
broadcasting the invalidate message to each processor in the cluster.

4 more elements

A multiprocessor system, comprising:

a main memory configured to store data;
a plurality of processors, each processor coupled to at least one memory cache;
a memory directory controller employing directory-based cache coherence;
at least one input/output device coupled to at least one processor;
a share mask comprising a data register for tracking shared copies of data blocks that are distributed from the main memory to one or more cache locations;
and
a PID-SHIFT register which stores configuration settings to determine which one of several shared data invalidation schemes shall be implemented;
wherein when the PID-SHIFT register contains a value of zero, the data bits in the share mask data register correspond to one of the plurality of processors and wherein when the PID-SHIFT register contains a nonzero value, the data bits in the share mask data register correspond to a cluster of processors, each cluster comprising more than one of the plurality of processor.

5 more elements

A multiprocessor system, comprising:

a memory;
multiple computer processor nodes, each with an associated memory cache;
and
a memory controller employing a directory-based cache coherency employing shared memory invalidation method, wherein:
the nodes are grouped into clusters;
the memory controller distributes memory blocks from the memory to the various cache locations at the request of the associated nodes;
upon receiving a request for exclusive ownership of one of the shared memory blocks, the memory controller distributes invalidate messages via direct point to point transmission to only those clusters containing nodes that share a block of data in the associated cache;
and
wherein when the invalidate message is received by a cluster, an invalidate message is broadcast to all nodes in the cluster.

6 more elements

Dependencies are inferred from the claim text.

Broadcast invalidate scheme

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Broadcast invalidate scheme

Life of this patent

Abstract

Claims20