Cache flushing
AssigneeIntel Corporation
InventorsJohn W. Horrigan, Namasivayam Thangavelu, Varghese George, Brian Holscher
Life of this patent
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Abstract
Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.
Claims30
A method of flushing a cache comprising:
- flushing a first portion of the cache;
- performing an operation other than a cache flush;
- and
- flushing a second portion of the cache.
A method of transitioning a processor from one operating mode to a second operating mode comprising:
- flushing a first portion of a cache;
- disabling the first portion;
- flushing a second portion of the cache;
- transitioning from the one operating mode to the second operating mode;
- and
- enabling the disabled portions of the cache.
A method of flushing a cache comprising:
- configuring a processor to flush a selected portion of a cache in response to a cache flush command, the selected portion being smaller than the entire cache;
- accepting the cache flush command;
- flushing the selected portion of the cache;
- reconfiguring the processor to flush enabled portions of the cache in response to the cache flush command;
- disabling the selected portion of the cache.
A method of flushing a cache coupled to a processor comprising interleaving cache flush operations of different portions of a cache with other processor operations.
A method for a peripheral to access a memory coupled to a cache, the method comprising:
- receiving a signal from the peripheral that it requires access to the memory;
- flushing a first portion of the cache;
- granting the peripheral access to the memory;
- flushing a second portion of the cache after the peripheral has accessed the memory.
A processor system comprising:
- a processor;
- a memory;
- a cache controller;
- a cache coupled to the processor and the memory, wherein a first portion of the cache is flushed in response to a cache flush command from the processor.
A method of flushing a cache hierarchy having multiple caches comprising:
- flushing a first portion of the cache hierarchy;
- performing an operation other than a cache flush;
- and
- flushing a second portion of the cache hierarchy, the second portion being no greater than an entire cache.
A computer system comprising:
- a processor operable in at least a first state and a second state;
- a memory;
- a cache controller;
- a cache coupled to the processor and the memory, the cache having at least two portions, each portion being adapted to independently flush.
A method of flushing a cache comprising:
- flushing at least a portion of a cache in response to a cache flush command;
- receiving a flush abort signal;
- aborting the flushing in response to the flush abort signal;
- storing an indicator indicative of the portion of the cache flushed prior to the aborting.
Dependencies are inferred from the claim text.