Cache management system
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.
Claims67
A cache memory system comprising:
- a main memory configured to hold at least one data entry in a first location;
- a cache memory comprising:
- a cache data memory configured to hold the data entry;
- and
- a cache tag memory configured to store a first main memory address of the data entry;
- and
- a processor configured to reassign the data entry from the first location to a second location in the main memory by overwriting the cache tag memory with a second main memory address without modifying the data entry in the cache data memory.
A method of reassigning data from a first memory location to a second memory location comprising writing a value to an entry in a cache tag memory without changing the content of an entry in a cache data memory associated with said entry in said cache tag memory.
A cache memory system for performing virtual data movement within a digital processing system, the system comprising:
- a main memory configured to hold at least one data string in a first location;
- a cache memory comprising:
- a cache data memory configured to hold the data string;
- and
- a cache tag memory associated with the cache data memory, the cache tag memory configured to store a first main memory address corresponding to the first location of the data string;
- and
- a processor configured to receive an instruction to move the data string from the first location to a second location in the main memory, the processor being further configured to overwrite the cache tag memory with a second main memory address without modifying the data string in the cache data memory.
A method for virtual data movement in a cache memory system within a digital processing system, the method comprising:
- storing a data string in a first main memory location;
- storing the data string in a cache data memory;
- storing in a cache tag memory a first address corresponding to the first main memory location;
- receiving an instruction to move the data string from the first main memory location to a second main memory location;
- and
- overwriting the cache tag memory with a second address corresponding to the second main memory location without changing the content of the data string in the cache data memory.
A cache system comprising:
- main memory means for storing a data entry at a first main memory location;
- cache memory means for storing the data entry;
- cache tag means for storing the first main memory location of the data entry;
- and
- processing means for receiving an instruction to move the data entry from the first main memory location to a second main memory location, said processing means configured to overwrite the first main memory location in the cache tag means with the second main memory location in response to receiving said instruction without moving the data entry in the cache memory means.
A method for data manipulation in a digital processing system, the method comprising:
- storing a block of data at a first series of addresses in a main memory;
- storing the block of data in multiple cache lines of a cache data memory;
- storing in a cache tag memory associated with the cache data memory the first series of addresses corresponding to the location of the block of data in the main memory;
- receiving an instruction with a processor to move the block of data from the first series of addresses to a second series of addresses in the main memory;
- and
- overwriting the cache tag memory with the second series of addresses without changing the content of the block of data in the cache data memory.
Dependencies are inferred from the claim text.