Data processing processor

A data processing processor including a bus arbitration apparatus for selecting one channel with respect to bus use requests issued from a plurality of channels and for allowing the selected channel to use the bus,

• said bus arbitration apparatus comprising:
• a first type of timer provided with respect to a channel having a high necessity of a real-time processing operation, and responsive to a bus use request notified with respect to a channel having the high necessity of the real-time processing operation, for counting a count value indicative of bus use permission time given to said channel having the high necessity of the real-time processing operation;
• a second type of timer provided with respect to a channel having a low necessity of a real-time processing operation, and for stopping a counting operation of the own timer with either a value larger than an initial value of the count time of said first type of timer with respect to the channel having the high necessity of the real-time processing operation or a value smaller than said initial value of the count time thereof;
• and
• a control circuit for comparing the count value of the first type timer with the value of the second type timer, for the respective channels, and allowing one channel having either a small value or a large value in the comparison result to use the bus at bus arbitration.

A data processing processor including a bus arbitration apparatus for selecting one channel with respect to bus use requests issued from a plurality of channels and for allowing the selected channel to use the bus, said bus arbitration apparatus comprising:

• a timer responsive to a bus use request notified with respect to a channel having a high priority order, for counting a count value indicative of bus use permission time given to said channel having the high priority order;
• a register for setting either a value larger than a maximum value of the count time of said timer or another value smaller than a minimum value of the count time thereof with respect to a channel having a priority order;
• and
• a control circuit for comparing the count value of the timer with the value of the register, for the respective channels, and allowing one channel having either a small value or a large value in the comparison result to use the bus at bus arbitration.

A data processing processor containing a bus arbitration apparatus for selecting one channel with respect to bus use requests issued from a plurality of channels and for allowing the selected channel to use the bus,

• said bus arbitration apparatus comprising:
• a first type of timer provided with respect to a channel having a high priority order, and responsive to a bus use request notified with respect to a channel having the high priority order, for counting a count value indicative of bus use permission time given to said channel having the high priority order;
• a second type of timer provided with respect to a channel having a low priority order, and for stopping a counting operation of the own timer with either a value larger than an initial value of the count time of said first type of timer with respect to the channel having the high priority order or a value smaller than said initial value of the count time thereof;
• and
• a control circuit for comparing the count value of the first type timer with the count value of the second type timer, for the respective channels, and allowing one channel having either a small value or a large value in the comparison result to use the bus at bus arbitration.