# US 2004/0073623 A1 · Pipelining cache-coherence operations in a shared-memory multiprocessing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2004/0073623 A1 - Document ID: US20040073623A1 - Status: Published application - Kind: A1 - Application number: 10/256,610 - Filed: 2002-09-27 - Published: 2004-04-15 - Earliest claimed: 2002-09-27 - Assignees: Apple Computer, Inc. - Inventors: Jack Benkual; William C. Athas; Joseph P. Bratt; Ronald Ray Hochsprung - Web page: https://patentgrep.com/patent/US20040073623A1 ## CPC - G06F 13/1615: {using a concurrent pipeline structrure} - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One embodiment of the present invention provides a system that facilitates pipelining cache coherence operations in a shared memory multiprocessor system. During operation, the system receives a command to perform a memory operation from a processor in the shared memory multiprocessor system. This command is received at a bridge that is coupled to the local caches of the processors in the shared memory multiprocessor system. If the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, the system delays the command until the in-progress pipelined cache coherency operation completes. Otherwise, the system reflects the command to local caches of other processors in the shared memory multiprocessor system. The system then accumulates snoop responses from the local caches of the other processor and sends the accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system. ## Claims ### Claim 1 A method for pipelining cache coherence operations in a shared memory multiprocessor system, comprising: receiving a command to perform a memory operation from a processor in the shared memory multiprocessor system; wherein the command is received at a coherence circuit that is coupled to local caches of processors in the shared memory multiprocessor system; and if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, delaying the command until the in-progress pipelined cache coherency operation completes. ### Claim 2 (depends on 1) The method of claim 1, wherein if the command is not directed to a cache line that is subject to an in-progress pipelined cache coherency operation, the method further comprises: reflecting the command to local caches of other processors in the shared memory multiprocessor system; accumulating snoop responses from the local caches of other processors; and sending an accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system. ### Claim 3 (depends on 2) The method of claim 2, wherein upon reflecting the command, the method further comprises storing an address associated with the command in a memory within the coherence circuit. ### Claim 4 (depends on 3) The method of claim 3, wherein determining if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation involves comparing a received address with addresses of in-progress pipelined cache coherency operations stored in the memory within the coherence circuit. ### Claim 5 (depends on 3) The method of claim 3, further comprising removing the address from the memory within the coherence circuit when the command is complete. ### Claim 6 (depends on 1) The method of claim 1, further comprising: examining a pipeline bit within the command; and if the pipeline bit is not set, processing the command in a non-pipelined mode. ### Claim 7 (depends on 6) The method of claim 6, wherein processing the command in the non-pipelined mode further comprises: waiting for in-progress commands to complete; reflecting the command to local caches of other processors in the shared memory multiprocessor system; and resuming processing of subsequent commands. ### Claim 8 (depends on 6) The method of claim 6, wherein processing the command in the non-pipelined mode further comprises: reflecting the command to local caches of other processors in the shared memory multiprocessor system; waiting for in-progress commands including the command to complete; and resuming processing of subsequent commands. ### Claim 9 (depends on 6) The method of claim 6, wherein processing the command in the non-pipelined mode further comprises: waiting for in-progress commands to complete; reflecting the command to local caches of other processors in the shared memory multiprocessor system; waiting for the command to complete; and resuming processing of subsequent commands. ### Claim 10 (depends on 6) The method of claim 6, wherein processing the command in the non-pipelined mode further comprises: examining a memory within the coherence circuit to determine if an in-progress command is being processed in the non-pipelined mode; and if so, waiting for the in-progress command being processed in the non-pipelined mode to complete before reflecting the command to local caches of other processors in the shared memory multiprocessor system. ### Claim 11 An apparatus for pipelining cache coherence operations in a shared memory multiprocessor system, comprising: a receiving mechanism that is configured to receive a command to perform a memory operation from a processor in the shared memory multiprocessor system; wherein the receiving mechanism is located in a coherence circuit that is coupled to local caches of processors in the shared memory multiprocessor system; and a delaying mechanism that is configured to delay the command until an in-progress pipelined cache coherency operation completes if the command is directed to a cache line that is subject to the in-progress pipelined cache coherency operation. ### Claim 12 (depends on 11) The apparatus of claim 11, further comprising: a reflecting mechanism that is configured to reflect the command to local caches of other processors in the shared memory multiprocessor system; an accumulating mechanism that is configured to accumulate snoop responses from the local caches of other processors; and a sending mechanism that is configured to send an accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system. ### Claim 13 (depends on 12) The apparatus of claim 12, further comprising a storing mechanism that is configured to store an address associated with the command in a memory within the coherence circuit. ### Claim 14 (depends on 13) The apparatus of claim 13, further comprising a comparing mechanism that is configured to compare a received address with addresses of in-progress pipelined cache coherency operations stored in the memory within the coherence circuit to determine if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation. ### Claim 15 (depends on 13) The apparatus of claim 13, further comprising a removing mechanism that is configured to remove the address from the memory within the coherence circuit when the command is complete. ### Claim 16 (depends on 11) The apparatus of claim 11, further comprising: an examining mechanism that is configured to examine a pipeline bit within the command; and a processing mechanism that is configured to process the command in a non-pipelined mode if the pipeline bit is not set. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising: a waiting mechanism that is configured to wait for in-progress commands to complete; a reflecting mechanism that is configured to reflect the command to local caches of other processors in the shared memory multiprocessor system; and a resuming mechanism that is configured to resume processing of subsequent commands. ### Claim 18 (depends on 16) The apparatus of claim 16, further comprising: a reflecting mechanism that is configured to reflect the command to local caches of other processors in the shared memory multiprocessor system; a waiting mechanism that is configured to wait for in-progress commands including the command to complete; and a resuming mechanism that is configured to resume processing of subsequent commands. ### Claim 19 (depends on 16) The apparatus of claim 16, further comprising: a waiting mechanism that is configured to wait for in-progress commands to complete; a reflecting mechanism that is configured to reflect the command to local caches of other processors in the shared memory multiprocessor system; wherein the waiting mechanism that is configured to wait for the command to complete; and a resuming mechanism that is configured to resume processing of subsequent commands. ### Claim 20 (depends on 16) The apparatus of claim 16: wherein the examining mechanism is further configured to examine a memory within the coherence circuit to determine if an in-progress command is being processed in the non-pipelined mode; and a waiting mechanism that is configured to wait for the in-progress command being processed in the non-pipelined mode to complete before reflecting the command to local caches of other processors in the shared memory multiprocessor system if an in-progress command is being processed in the non-pipelined mode. ### Claim 21 (depends on 11) The apparatus of claim 11, wherein the coherence circuit is located within a bridge chip that couples processors with memory. ### Claim 22 An apparatus for pipelining cache coherence operations in a shared memory multiprocessor system, comprising: a receiving mechanism that is configured to receive a command to perform a memory operation from a processor in the shared memory multiprocessor system; wherein the receiving mechanism is located in a bridge that is coupled to local caches of processors in the shared memory multiprocessor system; a comparing mechanism that is configured to compare an address within the command with addresses stored in a memory within the bridge to determine if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation; a reflecting mechanism that is configured to reflect the command to local caches of other processors in the shared memory multiprocessor system; an accumulating mechanism that is configured to accumulate snoop responses from local caches of other processors; a sending mechanism that is configured to send an accumulated snoop response to local caches of other processors in the shared memory multiprocessor system; and a delaying mechanism that is configured to delay the command until an in-progress pipelined cache coherency operation completes if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation.