Hardware extension for accelerating fractional integer division within 3D graphics and MP3 applications
AssigneeTexas Instruments Incorporated
InventorJean-Pierre Giacalone
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Abstract
An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.
Claims20
A data processing apparatus, comprising:
- a random access memory;
- a hardware accelerator coupled to said random access memory;
- and
- a digital signal processor (DSP) coupling said hardware accelerator to said random access memory, said hardware accelerator enabling said digital signal processor (DSP) to perform high speed division operations.
A data processing apparatus, comprising:
- a digital signal processor (DSP) enabled to perform high speed divisions operations in no more than two cycles per division.
The telecommunication device, comprising:
- a random access memory;
- a hardware accelerator coupled to said random access memory;
- digital circuitry coupling said hardware accelerator to said random access memory, said hardware accelerator enabling said digital circuitry to perform high speed division operations;
- analog circuitry;
- RF circuitry coupling said analog circuitry and said digital circuitry to an antenna;
- and
- a power source connected said RF, analog and digital circuitry.
A method, comprising the steps of:
- providing a processor;
- and
- performing a division operation associated with said processor in two cycles.
Dependencies are inferred from the claim text.