US 2004/0073418 A1 · Method and system for modeling of effective capacitance in logic circuits

Abstract

A method and system for modeling effective capacitance of logic circuits provides accuracy without iteration and an improved understanding of logical circuit block performance variation with implementation changes. An effective output capacitance of a logical circuit output node is calculated. The equivalent resistance of the output node is determined by modeling at least one of the output transistors using a transfer conductance model relating the input voltage function to the output current. The values in a pi-network model of the output impedance are determined from circuit design parameters relating the distributed resistance to the equivalent resistance of the output transistor and relating the distributed capacitance of the output transistor and relating the distributed capacitance to the two capacitances in the pi-network. The effective output then capacitance is determined by equating the time delays of the pi-network model and a simple parallel RC combination.

Claims24

Dependent claims

A method for modeling output node characteristics of a logical circuit block, comprising:

determining a lumped capacitance (CL) at said output node from design parameters of said logical circuit block;
determining an equivalent output resistance of an output node transistor (RN or RP) from said design parameters;
modeling a first model circuit of said output node, said first model circuit representing a distribution of said lumped capacitance;
equating a first time delay of said first model circuit to a second time delay of a second model RC circuit consisting of a resistance equal to said equivalent resistance in parallel with a capacitance equal to an effective capacitance;
and
solving for said effective capacitance from a result of said equating.

3 more elements

A computer program product for use with a workstation computer, wherein said computer program product comprises signal bearing media containing program instructions for execution within said workstation computer for modeling output node characteristics of a logical circuit block, wherein said program instructions comprise program instructions for:

determining a lumped capacitance (CL) at said output node from design parameters of said logical circuit block;
determining an equivalent output resistance of an output node transistor (RN or RP) from said design parameters;
modeling a first model circuit of said output node, said first model circuit representing a distribution of said lumped capacitance;
equating a first time delay of said first model circuit to a second time delay of a second model RC circuit consisting of a resistance equal to said equivalent resistance in parallel with a capacitance equal to an effective capacitance;
and
solving for said effective capacitance from a result of said equating.

3 more elements

A workstation comprising:

a memory for storing program instructions and data values for modeling characteristics of a logical circuit block;
a processor for executing said program instructions, wherein said program instructions comprise program instructions for
determining a lumped capacitance (CL) at said output node from design parameters of said logical circuit block;
determining an equivalent output resistance of an output node transistor (RN or RP) from said design parameters;
modeling a first model circuit of said output node, said first model circuit representing a distribution of said lumped capacitance;
equating a first time delay of said first model circuit to a second time delay of a second model RC circuit consisting of a resistance equal to said equivalent resistance in parallel with a capacitance equal to an effective capacitance;
and
solving for said effective capacitance from a result of said equating.

5 more elements

Dependencies are inferred from the claim text.

Method and system for modeling of effective capacitance in logic circuits

Life of this patent

Method and system for modeling of effective capacitance in logic circuits

Life of this patent

Abstract

Claims24