Overflow predictive arithmetic instruction optimization using chaining

A method for arithmetic expression optimization, comprising:

• step for receiving a first instruction defined for a first processor having a first base, said instruction comprising an operator and at least one operand having an operand type;
• step for converting said first instruction to a second instruction optimized for a second processor having a second base when overflow is not possible based at least in part on said operator and the relationship between said operand type and said second base, said second base smaller than said first base;
• and
• step for converting instructions in a chain of instructions to a wider base when said at least one operand carries the potential for overflow beyond said second base and when said operator is sensitive to overflow, said chain bounded by said second instruction and a third instruction that is the source of potential overflow associated with said at least one operand, said third instruction having been previously optimized, said wider base larger than said second base and smaller or equal to said first base.

A program storage device readable by a machine, embodying a program of instructions executable by the machine to perform a method for arithmetic expression optimization, the method comprising:

• receiving a first instruction defined for a first processor having a first base, said instruction comprising an operator and at least one operand having an operand type;
• converting said first instruction to a second instruction optimized for a second processor having a second base when overflow is not possible based at least in part on said operator and the relationship between said operand type and said second base, said second base smaller than said first base;
• and
• converting instructions in a chain of instructions to a wider base when said at least one operand carries the potential for overflow beyond said second base and when said operator is sensitive to overflow, said chain bounded by said second instruction and a third instruction that is the source of potential overflow associated with said at least one operand, said third instruction having been previously optimized, said wider base larger than said second base and smaller or equal to said first base.

An apparatus for arithmetic expression optimization, comprising:

• means for receiving a first instruction defined for a first processor having a first base, said instruction comprising an operator and at least one operand having an operand type;
• means for converting said first instruction to a second instruction optimized for a second processor having a second base when overflow is not possible based at least in part on said operator and the relationship between said operand type and said second base, said second base smaller than said first base;
• and
• means for converting instructions in a chain of instructions to a wider base when said at least one operand carries the potential for overflow beyond said second base and when said operator is sensitive to overflow, said chain bounded by said second instruction and a third instruction that is the source of potential overflow associated with said at least one operand, said third instruction having been previously optimized, said wider base larger than said second base and smaller or equal to said first base.

A method of using an application software program including arithmetic expression optimization of at least one instruction targeted to a processor, the method comprising:

• receiving the software program on said processor, said software program optimized according to a method comprising:
• receiving a first instruction defined for a first processor having a first base, said instruction comprising an operator and at least one operand having an operand type;
• converting said first instruction to a second instruction optimized for a second processor having a second base when overflow is not possible based at least in part on said operator and the relationship between said operand type and said second base, said second base smaller than said first base;
• and
• converting instructions in a chain of instructions to a wider base when said at least one operand carries the potential for overflow beyond said second base and when said operator is sensitive to overflow, said chain bounded by said second instruction and a third instruction that is the source of potential overflow associated with said at least one operand, said third instruction having been previously optimized, said wider base larger than said second base and smaller or equal to said first base;
• and
• executing said at least one instruction on said processor.

A smart card having a microcontroller embedded therein, said microcontroller configured to execute a virtual machine, the virtual machine capable of executing a software application comprising a plurality of previously optimized instructions, the instructions optimized by a method comprising:

• receiving the software program on said processor, said software program optimized according to a method comprising:
• receiving a first instruction defined for a first processor having a first base, said instruction comprising an operator and at least one operand having an operand type;
• converting said first instruction to a second instruction optimized for a second processor having a second base when overflow is not possible based at least in part on said operator and the relationship between said operand type and said second base, said second base smaller than said first base;
• and
• converting instructions in a chain of instructions to a wider base when said at least one operand carries the potential for overflow beyond said second base and when said operator is sensitive to overflow, said chain bounded by said second instruction and a third instruction that is the source of potential overflow associated with said at least one operand, said third instruction having been previously optimized, said wider base larger than said second base and smaller or equal to said first base.