Method for monitoring end of life for battery

A pacemaker, including:

• a battery power terminal for a pacemaker battery;
• a capacitor electrically connected to the battery power terminal;
• pacemaker control circuitry electrically connected to the battery power terminal and the capacitor for controlling current flow from the battery power terminal to the capacitor to charge the capacitor and to discharge the capacitor to a discharge voltage level (Vd) before beginning a time charge measurement;
• and
• charge time measurement (CTM) control circuitry electrically connected to the pacemaker control circuitry and adapted to:
• access a predetermined set of charge time measurement set-up parameters and a predetermined elective replacement time (ERT) charge time limit associated with an AC impedance target for the battery;
• determine a rate of charge storage in the capacitor using the predetermined set of charge time measurement set-up parameters;
• and
• declare an ERT using the determined rate of charge storage in the capacitor and the ERT charge time limit,
• wherein the predetermined set of charge time measurement set-up parameters to be accessed by the CTM control circuitry include:
• a final voltage (VF) to end the charge time measurement for determining the rate of charge storage in the capacitor;
• and
• an initial reference voltage (VI) to begin the charge time measurement for determining the rate of charge storage in the capacitor, VI being greater than Vd.

A pacemaker, including:

• a battery power terminal for a pacemaker battery;
• a pacing supply storage (PSS) capacitor;
• pacemaker control circuitry, including:
• a switch capacitor power supply having an input connected to the battery terminal, an output connected to the PSS capacitor, and a clock input to enable the switch capacitor power supply to charge the PSS capacitor;
• a clock signal line, a Vstop reference potential line, and a selectable reference potential (Vx) line;
• a first comparator having a first input electrically connected to the battery power terminal, a second input connected to the Vstop reference potential line;
• and an output;
• a second comparator having a first input connected to the selectable reference potential line, a second input connected to the output of the switch capacitor power supply, and an output;
• and
• at least one logic gate, including a first input connected to the output from the first comparator, a second input connected to the output from the second comparator, a third input connected to the clock signal line, and an output connected to the clock input of the switch capacitor power supply;
• a discharge switch connected to the PSS capacitor;
• sensing and pace control circuitry connected to the battery power terminal;
• and
• charge time measurement (CTM) control circuitry, including:
• a number of registers to hold a Vd value corresponding to a desired discharge voltage for the PSS capacitor, a VI value corresponding to an initial voltage across the PSS capacitor to begin a time charge measurement, and a VF value corresponding to a final voltage across the PSS capacitor to end the time charge measurement;
• a multiplexer having an output, the multiplexer being operably connected to the number of registers to selectively pass one of the Vd, VI and VF values to the output of the multiplexer;
• a D/A converter connected to the output of the multiplexer to convert the selected one of the Vd, VI and VF values to a potential on the selectable reference potential (Vx) line for comparison to the output of the switch capacitor power supply by the second comparator;
• and
• a control circuit connected to the multiplexer to select one of the Vd, VI and VF values to appropriately control the switch capacitor power supply to charge the PSS capacitor from the discharge voltage to the initial voltage and from the initial voltage to the final voltage, the control circuit being connected to the discharge switch to selectively discharge the PSS capacitor from the final voltage to the desired discharge voltage, the control circuit being connected to the clock signal line, the control circuit including circuitry to determine a rate of charge storage in the PSS capacitor from the initial voltage to the final voltage, and estimate battery depletion based on the rate of charge storage in the PSS capacitor.

A system, comprising:

• a battery power terminal for a battery;
• a capacitor electrically connected to the battery power terminal;
• means to control current flow from the battery power terminal to charge the capacitor;
• means to access a predetermined set of charge time measurement set-up parameters and a predetermined elective replacement time (ERT) charge time limit associated with an AC impedance target for the battery, the predetermined set of charge time measurement set-up parameters including:
• a final voltage (VF) to end a charge time measurement for determining the rate of charge storage in the capacitor;
• an initial reference voltage (VI) to begin the charge time measurement for determining the rate of charge storage in the capacitor;
• and
• a voltage level (Vd) to which the capacitor is discharged prior to beginning the time measurement for determining the rate of charge storage in the capacitor, Vd being less than VI;
• means to determine a rate of charge storage in the capacitor using the predetermined set of charge time measurement set-up parameters;
• means to compare the determined rate of charge storage in the capacitor to the predetermined ERT charge time limit for the predetermined set of charge time measurement set-up parameters;
• and
• means to declare an ERT based on a number of comparisons between the determined rate of charge storage in the capacitor and the ERT charge time limit.