Semiconductor device and method of fabricating the same
AssigneeSeiko Epson Corporation
InventorSusumu Inoue
Life of this patent
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Abstract
A semiconductor device having a memory region formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each nonvolatile memory device has a word gate formed above a semiconductor layer with a gate insulating layer interposed, an impurity layer formed in the semiconductor layer to form a source region or a drain region, and control gates formed in the form of side walls formed along both side surfaces of the word gate. Each control gate includes a first control gate and a second control gate in mutual contact, where the first and second control gates are respectively formed on charge accumulation layers of different thicknesses.
Claims10
A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns,
- wherein each of the non-volatile memory devices has:
- a word gate formed above a semiconductor layer with a gate insulating layer interposed;
- an impurity layer formed in the semiconductor layer to form a source region or a drain region;
- and
- control gates in the form of side walls formed along both side surfaces of the word gate;
- wherein each of the control gates includes a first control gate and a second control gate in mutual contact;
- wherein a first insulating layer is disposed between the first control gate and the semiconductor layer, and a side insulating layer is disposed between the first control gate and the word gate;
- wherein a second insulating layer is disposed between the second control gate and the semiconductor layer;
- and
- wherein the thickness of the first insulating layer is larger than the thickness of the second insulating layer.
A method of fabricating a semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns, the method comprising:
- (a) forming a gate insulating layer above a semiconductor layer;
- (b) forming a first conductive layer above the gate insulating layer;
- (c) forming a stopper layer above the first conductive layer;
- (d) patterning the stopper layer and the first conductive layer to form a stack of layers formed of that stopper layer and that first conductive layer;
- (e) forming a first insulating layer at least above the semiconductor layer and along both side surfaces of the first conductive layer;
- (f) forming a second conductive layer over the entire surface of the memory region, and forming side-wall-shaped first control gates on the semiconductor layer and on both side surfaces of the first conductive layer by anisotropic etching of the second conductive layer, with the first insulating layer interposed;
- (g) using the first control gates as masks to remove part of the first insulating layer, and defining part of the remaining first insulating layer under the removed portion as a second insulating layer;
- (h) forming a third conductive layer over the entire surface of the memory region, and forming a second control gate on the semiconductor layer and on a side surface of each of the first control gates by anisotropic etching of the third conductive layer, with the second insulating layer interposed;
- (i) forming an impurity layer in the semiconductor layer to form a source region or a drain region;
- (j) forming a third insulating layer over the entire surface of the memory region and removing part of the third insulating layer to expose part of the stopper layer;
- and
- (k) removing the stopper layer, forming a fourth conductive layer over the entire surface of the semiconductor layer, and then patterning the fourth conductive layer to form a word line.
Dependencies are inferred from the claim text.