High rate receiver
AssigneeOki Techno Centre (Singapore) Pte Ltd
InventorWenzhen Li
Life of this patent
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Abstract
The present invention relates to wireless burst communications receivers especially for high-rate indoor applications. The present invention provides a phase lock loop (PLL) circuit for receiving a burst signal including a repeated preamble sequence and a data sequence, the circuit comprising a maximum likelihood sequence estimator (MLSE) and means for determining the phase difference between a signal at the output of the MLSE and a corresponding delayed signal at the input of the MLSE, phase rotating means for rotating the phase of said burst signal dependent on said phase difference, the output of said means being coupled to the MLSE input, wherein the phase determining means is further arranged to determine the phase difference between a non-delayed signal at the MLSE input and a stored preamble sequence signal.
Claims11
A phase lock loop (PLL) circuit for receiving a burst signal including a repeated preamble sequence and a data sequence;
- the circuit comprising:
- a maximum likelihood sequence estimator (MLSE) and means for determining the phase difference between a signal at the output of the MLSE and a corresponding delayed signal at the input of the MLSE;
- phase rotating means for rotating the phase of said burst signal dependent on said phase difference, the output of said means being coupled to the MLSE input;
- wherein the phase determining means is further arranged to determine the phase difference between a non-delayed signal at the MLSE input and a stored preamble sequence signal.
A carrier recovery architecture for receiving a burst signal including a repeated training sequence and a data sequence;
- the architecture comprising:
- a PLL having a mixer which receives a signal, an MLSE having an input coupled to the mixer, and a phase detector, the phase detector arranged to determine the phase difference between a signal at an output of the MLSE and a corresponding delayed signal at the MLSE input;
- the PLL further having mixer input means which is arranged to provide a rotating signal to the mixer in order to adjust the frequency of the received signal which the mixer outputs to the MLSE, said rotating signal being dependent on said phase difference;
- wherein the phase detector is arranged to be switch-able between said MLSE output and a training sequence memory, and between said MLSE delayed input and a non-delayed MLSE input.
A phase detector having an input coupled to the output of a maximum likelihood sequence estimator (MLSE) and a second input coupled to the input of said MLSE;
- the detector comprising:
- delay means for delaying the second input signal by a delay time corresponding to the processing delay of the MLSE;
- processing means arranged to determine the phase difference between the first and delayed second inputs;
- the processing means arranged to determine the imaginary part of the result of dividing the second input by the first input;
- said part corresponding to the phase difference.
Dependencies are inferred from the claim text.