# US 2004/0071033 A1 · Enhanced protection for input buffers of low-voltage flash memories

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- Number: US 2004/0071033 A1
- Document ID: US20040071033A1
- Status: Published application
- Kind: A1
- Application number: 10/673,756
- Filed: 2003-09-29
- Published: 2004-04-15
- Earliest claimed: 2000-08-30
- Assignees: Micron Technology, Inc.
- Inventors: Giulio-Giuseppe Marotta; Elio D'Ambrosio
- Web page: https://patentgrep.com/patent/US20040071033A1

## CPC

- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- H03K 19/00315: {in field-effect transistor circuits}
- G11C 2207/2227: Standby or low power modes
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

## Claims

### Claim 1

A system to enhance buffering low-voltage flash memory, comprising:
a multiple of thin gate-oxide transistors; and
an input buffer receptive to an enabling signal, an input signal, and an inhibiting signal, wherein the input buffer includes a component that inhibits semiconductor breakdown of the multiple of thin gate-oxide transistors when the inhibiting signal is at a low voltage level.

### Claim 2 (depends on 1)

The system of claim 1, wherein the component includes a first connection, a second connection, and a third connection, wherein the first connection is coupled to the inhibiting signal, wherein the second connection is coupled to the input signal, wherein the third connection presents the input signal when the inhibiting signal is at a first predetermined level.

### Claim 3 (depends on 2)

The system of claim 2, wherein the third connection of the component refrains from presenting the input signal when the inhibiting signal is at a second predetermined level so as to inhibit semiconductor breakdown of the multiple of thin gate-oxide transistors when the input signal is at an undesired high voltage level.

### Claim 4 (depends on 1)

The system of claim 1, further comprising a voltage sensor receptive to the input signal and a pumped signal, wherein the voltage sensor produces a sensed signal at a third predetermined level when the input signal is at a desired high voltage level, otherwise the voltage sensor produces the sensed signal at a fourth predetermined level.

### Claim 5 (depends on 4)

The system of claim 4, further comprising an inhibiting circuit receptive to the pumped signal and the sensed signal, wherein the inhibiting circuit produces the inhibiting signal.

### Claim 6

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a first connection, a second connection, and a third connection, wherein the first connection is receptive to an inhibiting signal, wherein the second connection is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the third connection when the inhibiting signal is at a predetermined level; and
an output stage having a first connection and a second connection, wherein the first connection is coupled to the third connection of the input stage, and wherein the second connection presents the input signal to the low-voltage flash memory device.

### Claim 7 (depends on 6)

The input buffer of claim 6, further comprising a resistor coupled to the second connection of the input stage, wherein the resistor limits a current when the input signal comprises a signal generated from an electrostatic discharge.

### Claim 8 (depends on 7)

The input buffer of claim 7, further comprising a first clamping circuit coupled to the resistor to clamp the input signal to a voltage supply, wherein the first clamping circuit enhances an electrostatic-discharge test that is applied to the low-voltage memory device.

### Claim 9 (depends on 7)

The input buffer of claim 7, further comprising a second clamping circuit coupled to the resistor to clamp the input signal to ground, wherein the second clamping circuit enhances an electrostatic-discharge test that is applied to the low-voltage memory device.

### Claim 10 (depends on 7)

The input buffer of claim 7, further comprising a third clamping circuit coupled to the third connection of the input stage to clamp the input signal being presented at the third connection of the input stage to a voltage supply, wherein the third clamping circuit enhances a charge-device-model test that is applied to the low-voltage memory device.

### Claim 11 (depends on 7)

The input buffer of claim 7, further comprising a fourth clamping circuit coupled to the third connection of the input stage to clamp the input signal being presented at the third connection of the input stage to ground, wherein the fourth clamping circuit enhances a charge-device-model test that is applied to the low-voltage memory device.

### Claim 12

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a predetermined level; and
an output stage having a first connection and a second connection, wherein the first connection is coupled to the source of the input stage, and wherein the second connection presents the input signal to the low-voltage flash memory device.

### Claim 13 (depends on 12)

The input buffer of claim 12, further comprising a first p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is receptive to the inhibiting signal, wherein the source is coupled to the source of the input stage, and wherein the bias is coupled to the source of the first p-channel transistor.

### Claim 14 (depends on 13)

The input buffer of claim 13, further comprising a second p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is receptive to the inhibiting signal, wherein the source is coupled to the drain of the first p-channel transistor, wherein the bias is coupled to the drain of the second p-channel transistor.

### Claim 15 (depends on 14)

The input buffer of claim 14, further comprising a resistor having a first connection and a second connection, wherein the first connection is coupled to the drain of the second p-channel transistor, wherein the second connection is coupled to a voltage supply.

### Claim 16 (depends on 15)

The input buffer of claim 15, wherein the coupling between the source of the first p-channel transistor and the drain of the input stage defines a node, wherein the first p-channel transistor and the second p-channel transistor act to prevent the node from floating when the inhibiting signal is at the predetermined level.

### Claim 17

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a predetermined level; and
an output stage having an inverter that includes a first connection and a second connection, wherein the first connection is coupled to the source of the input stage, and wherein the second connection presents the input signal to the low-voltage flash memory device.

### Claim 18 (depends on 17)

The input buffer of claim 17, wherein the inverter includes an n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the input stage, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal.

### Claim 19 (depends on 18)

The input buffer of claim 18, wherein the inverter further includes a p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the input stage, wherein the source is coupled to the, drain of the n-channel transistor.

### Claim 20 (depends on 19)

The input buffer of claim 19, further comprising an enabling transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the drain is coupled to a voltage supply, wherein the source is coupled to the drain of the p-channel transistor.

### Claim 21 (depends on 20)

The input buffer of claim 20, wherein the enabling transistor includes a p-channel transistor.

### Claim 22

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the transistor inhibits the input signal from being presented at the source when the inhibiting signal is at a first predetermined level;
an output stage having an inverter that includes a first connection and a second connection, wherein the first connection is coupled to the source of the transistor, and wherein the second connection presents the input signal to the low-voltage flash memory device; and
a voltage sensor to trigger when the input signal is at a second predetermined level, wherein the voltage sensor is receptive to a pumped signal and the input signal.

### Claim 23 (depends on 22)

The input buffer of claim 22, wherein the voltage sensor includes a triggering stage receptive to the input signal, wherein the triggering stage includes a first portion that has a set of p-channel transistors that includes:
a first p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to a first resistor, wherein the bias is coupled to the input signal, wherein the first resistor is coupled to a voltage supply;
a second p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to a second resistor, wherein the drain is coupled to the second resistor and the source of the first p-channel transistor, wherein the bias is coupled to the input signal;
a third p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to a third resistor, wherein the source is coupled to the input signal, wherein the drain is coupled to the third resistor and the source of the second p-channel transistor, and wherein the bias is coupled to the input signal; and
wherein the triggering stage includes a second portion that has a set of n-channel transistors that includes:
a first n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the pumped signal, wherein the source is coupled to ground;
a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the pumped signal, wherein the source is coupled to the drain of the first n-channel transistor;
a third n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the pumped signal, wherein the source is coupled to the drain of the second n-channel transistor;
a fourth n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the pumped signal, wherein the source is coupled to the drain of the third n-channel transistor;
a fifth n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the pumped signal, wherein the source is coupled to the drain of the fourth n-channel transistor; and
a sixth n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the pumped signal, wherein the drain is coupled to the source of the first p-channel transistor, and wherein the source is coupled to the drain of the fifth n-channel transistor.

### Claim 24 (depends on 23)

The input buffer of claim 23, further comprising a set of metal options that includes:
a first metal option having a first connection and a second connection, wherein the first connection is receptive to the input signal, and wherein the second connection is coupled to the source of the third p-channel transistor;
a second metal option having a first connection and a second connection, wherein the first connection is coupled to the source of the third p-channel transistor, and wherein the second connection is coupled to the drain of the third p-channel transistor;
a third metal option having a first connection and a second connection, wherein the first connection is coupled to the source of the second p-channel transistor, and wherein the second connection is coupled to the drain of the second p-channel transistor;
a fourth metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the fifth n-channel transistor, and wherein the second connection is coupled to the source of the fifth n-channel transistor;
a fifth metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the fourth n-channel transistor, and wherein the second connection is coupled to the source of the fourth n-channel transistor;
a sixth metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the third n-channel transistor, and wherein the second connection is coupled to the source of the third n-channel transistor;
a seventh metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the second n-channel transistor, and wherein the second connection is coupled to the source of the second n-channel transistor; and
an eighth metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the first n-channel transistor, and wherein the second connection is coupled to the source of the first n-channel transistor.

### Claim 25 (depends on 23)

The input buffer of claim 23, further comprising an inverting stage that includes:
a first inverting stage that includes:
a first inverter that includes:
a seventh n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the drain of the sixth n-channel transistor, wherein the source is coupled to ground;
a fourth p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to the gate of the seventh n-channel transistor, wherein the source is coupled to the voltage supply, wherein the drain is coupled to the drain of the seventh n-channel transistor, and wherein the bias is coupled to the voltage supply;
a second inverter that includes:
an eighth n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the drain of the seventh n-channel transistor, wherein the source is coupled to ground;
a fifth p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to the gate of the eighth n-channel transistor, wherein the source is coupled to the voltage supply, wherein the drain is coupled to the drain of the eighth n-channel transistor, and wherein the bias is coupled to the voltage supply;
a second inverting stage that includes:
a third inverter having a first connection and a second connection, wherein the first connection is coupled to the drain of the eighth n-channel transistor; and
a fourth inverter having a first connection and a second connection, wherein the first connection is coupled to the second connection of the third inverter.

### Claim 26 (depends on 25)

The input buffer of claim 25, further comprising a delay stage to reject undesired noise that includes:
a first delay circuit that includes:
a first metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the eighth n-channel transistor;
a second metal option having a first connection and a second connection, wherein the first connection is coupled to the voltage supply, wherein the second connection is coupled to the second connection of the first metal option;
a sixth p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the second connection of the first metal option, wherein the drain is coupled to the source, wherein the source is coupled to the voltage supply;
a second delay circuit that includes:
a third metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the eighth n-channel transistor;
a fourth metal option having a first connection and a second connection, wherein the first connection is coupled to ground, wherein the second connection is coupled to the second connection of the third metal option;
a ninth n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the second connection of the third metal option, wherein the drain is coupled to the source, wherein the source is coupled to ground;
a third delay circuit that includes:
a fifth metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the eighth n-channel transistor;
a sixth metal option having a first connection and a second connection, wherein the first connection is coupled to the voltage supply, wherein the second connection is coupled to the second connection of the fifth metal option;
a seventh p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the second connection of the fifth metal option, wherein the drain is coupled to the source, wherein the source is coupled to the voltage supply;
a fourth delay circuit that includes:
a seventh metal option having a first connection and a second connection, wherein the first connection is coupled to the drain of the eighth n-channel transistor;
an eighth metal option having a first connection and a second connection, wherein the first connection is coupled to ground, wherein the second connection is coupled to the second connection of the seventh metal option; and
a tenth n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the second connection of the seventh metal option, wherein the drain is coupled to the source, wherein the source is coupled to ground.

### Claim 27

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the transistor inhibits the input signal from being presented at the source when the inhibiting signal is at a first predetermined level;
an output stage having an inverter that includes a first connection and a second connection, wherein the first connection is coupled to the source of the transistor, and wherein the second connection presents the input signal to the low-voltage flash memory device; and
an inhibiting circuit to selectively produce the inhibiting signal, wherein the inhibiting circuit is receptive to a pumped signal and a sensed signal.

### Claim 28 (depends on 27)

The input buffer of claim 27, wherein the inhibiting circuit includes a first n-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to the sensed signal, wherein the drain presents the inhibiting signal, wherein the source is coupled to ground.

### Claim 29 (depends on 28)

The input buffer of claim 28, wherein the inhibiting circuit includes a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to an inverted sensed signal, wherein the source is coupled to ground.

### Claim 30 (depends on 29)

The input buffer of claim 29, wherein the inhibiting circuit includes a first p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to the drain of the second n-channel transistor, wherein the source is receptive to the pumped signal, wherein the drain is coupled to the drain of the first n-channel transistor, and wherein the bias is receptive to the pumped signal.

### Claim 31 (depends on 30)

The input buffer of claim 30, wherein the inhibiting circuit includes a second p-channel transistor having a gate, a drain, a source, and a bias, wherein the gate is coupled to the drain of the first n-channel transistor, wherein the source is receptive to the pumped signal, wherein the drain is coupled to the drain of the second n-channel transistor, and wherein the bias is receptive to the pumped signal.

### Claim 32

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a low level;
an output stage to present the input signal to the low-voltage flash memory device, wherein the output stage includes:
a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal;
a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain is coupled to the drain of the second n-channel transistor; and
a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor.

### Claim 33

An input buffer for a low-voltage flash memory device, comprising:
an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a low level;
an output stage to present the input signal to the low-voltage flash memory device, wherein the output stage includes:
a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal;
a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain is coupled to the drain of the second n-channel transistor; and
a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor;
a voltage sensor to trigger when the input signal is at a first high level, wherein the voltage sensor is receptive to a pumped signal and the input signal to produce a sensed signal; and
an inhibiting circuit to selectively produce the inhibiting signal, wherein the inhibiting circuit is receptive to the pumped signal and the sensed signal.

### Claim 34

A method for buffering a low-voltage flash memory device, comprising:
transferring by an input stage having a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a predetermined level; and
outputting by an output stage by inverting by an inverter that includes a first connection and a second connection, wherein the first connection is coupled to the source of the input stage, and wherein the second connection presents the input signal to the low-voltage flash memory device.

### Claim 35 (depends on 34)

The method of claim 34, wherein inverting includes the inverter that includes an n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the input stage, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal.

### Claim 36 (depends on 35)

The method of claim 35, wherein inverting includes the inverter that further includes a p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the input stage, wherein the drain is coupled to the drain of the n-channel transistor.

### Claim 37 (depends on 36)

The method of claim 36, further comprising enabling the inverter by an enabling transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the drain of the p-channel transistor.

### Claim 38 (depends on 37)

The method of claim 37, wherein enabling includes the enabling transistor that includes a p-channel transistor.

### Claim 39

A method for buffering a low-voltage flash memory device, comprising:
transferring by an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein transferring includes inhibiting the input signal from being presented at the source when the inhibiting signal is at a low level;
outputting by an output stage to present the input signal to the low-voltage flash memory device, wherein outputting includes:
receiving the input signal by a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents the input signal at a low level when the gate receives the input signal at a high level;
receiving the input signal by a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain presents the input signal at a high level when the gate receives the input signal at a low level; and
enabling the first p-channel transistor by a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to a low enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor.

### Claim 40 (depends on 39)

The method of claim 39, wherein the act of inhibiting occurs when the low-voltage flash memory device is inactivated.

### Claim 41

A method for buffering a low-voltage flash memory device, comprising:
transferring by an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage refrains from transferring the input signal from being presented at the source when the inhibiting signal is at a low level;
outputting by an output stage to present the input signal to the low-voltage flash memory device, wherein the output stage includes:
a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal;
a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain is coupled to the drain of the second n-channel transistor; and
a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor;
sensing by a voltage sensor to trigger when the input signal is at a first high level, wherein the voltage sensor is receptive to a pumped signal and the input signal to produce a sensed signal; and
producing by an inhibiting circuit that selectively produces the inhibiting signal, wherein the inhibiting circuit is receptive to the pumped signal and the sensed signal.

### Claim 42

A wireless device, comprising:
a processor;
a display; and
a low-voltage flash memory device that includes:
a multiple of thin gate-oxide transistors; and
an input buffer receptive to an enabling signal, an input signal, and an inhibiting signal, wherein the input buffer includes a component that inhibits semiconductor breakdown of the multiple of thin gate-oxide transistors when the inhibiting signal is at a predetermined level.

### Claim 43

An input buffer protection circuit comprising:
an input node to receive an input signal;
an internal signal node coupled to communicate the input signal to an input buffer circuit;
a pass transistor coupled between the input node and the internal signal node;
a bias circuit coupled to the internal signal node, wherein the bias circuit and the pass transistor are coupled to be controlled by an inhibitor signal such that the bias circuit is active to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node; and
control circuitry to provide the inhibitor signal.

### Claim 44 (depends on 43)

The input buffer protection circuit of claim 43 wherein the control circuitry comprises transistors to deactivate the pass transistor and to activate the bias circuit when the input signal reaches a predetermined threshold voltage level.

### Claim 45 (depends on 43)

The input buffer protection circuit of claim 43 wherein:
the pass transistor comprises an n-channel transistor comprising a gate coupled to receive the inhibitor signal, a drain, and a source; and
the bias circuit comprises a pair of p-channel transistors and a resistor coupled in series between a voltage supply and the internal signal node, gates of each of the pair of p-channel transistors being coupled to receive the inhibitor signal.

### Claim 46 (depends on 43)

The input buffer protection circuit of claim 43 wherein the control circuitry comprises:
a voltage sensor coupled to receive a pumped signal and the input signal, the voltage sensor to generate a sensed signal in response to the pumped signal and the input signal; and
an inhibiting circuit coupled to receive the pumped signal and coupled to the voltage sensor to receive the sensed signal, the inhibiting circuit being coupled to the pass transistor to generate the inhibitor signal in response to the pumped signal and the sensed signal.

### Claim 47

An integrated circuit comprising:
an input node to receive an input signal;
an internal signal node coupled to communicate the input signal to an input buffer circuit;
a pass transistor coupled between the input node and the internal signal node;
a bias circuit coupled to the internal signal node, wherein the bias circuit and the pass transistor are coupled to be controlled by an inhibitor signal such that the bias circuit is active to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node; and
control circuitry to provide the inhibitor signal to activate the pass transistor and deactivate the bias circuit while the input signal is less than a predetermined threshold voltage level, and to deactivate the pass transistor and activate the bias circuit when the input signal reaches the predetermined threshold voltage level.

### Claim 48 (depends on 47)

The integrated circuit of claim 47 wherein:
the pass transistor comprises an n-channel transistor comprising a gate coupled to receive the inhibitor signal, a drain, and a source; and
the bias circuit comprises a pair of p-channel transistors and a resistor coupled in series between a voltage supply and the internal signal node, gates of each of the pair of p-channel transistors being coupled to receive the inhibitor signal.

### Claim 49 (depends on 47)

The integrated circuit of claim 47 wherein the control circuitry comprises:
a voltage sensor coupled to receive a pumped signal and the input signal, the voltage sensor to generate a sensed signal in response to the pumped signal and the input signal; and
an inhibiting circuit coupled to receive the pumped signal and coupled to the voltage sensor to receive the sensed signal, the inhibiting circuit being coupled to the pass transistor to generate the inhibitor signal in response to the pumped signal and the sensed signal.

### Claim 50

A memory device comprising:
an input node to receive an input signal;
an internal signal node coupled to communicate the input signal to an input buffer circuit;
a pass transistor coupled between the input node and the internal signal node;
a bias circuit coupled to the internal signal node, wherein the bias circuit and the pass transistor are coupled to be controlled by an inhibitor signal such that the bias circuit is active to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node; and
control circuitry to provide the inhibitor signal to activate the pass transistor and deactivate the bias circuit while the memory device is in a non-test operation, and to deactivate the pass transistor and activate the bias circuit when the memory device is in a test mode indicated by an elevated voltage greater than a predetermined threshold voltage level provided on the input node.

### Claim 51 (depends on 50)

The memory device of claim 50 wherein:
the pass transistor comprises an n-channel transistor comprising a gate coupled to receive the inhibitor signal, a drain, and a source; and
the bias circuit comprises a pair of p-channel transistors and a resistor coupled in series between a voltage supply and the internal signal node, gates of each of the pair of p-channel transistors being coupled to receive the inhibitor signal.

### Claim 52 (depends on 50)

The memory device of claim 50 wherein the control circuitry comprises:
a voltage sensor coupled to receive a pumped signal and the input signal, the voltage sensor to generate a sensed signal in response to the pumped signal and the input signal; and
an inhibiting circuit coupled to receive the pumped signal and coupled to the voltage sensor to receive the sensed signal, the inhibiting circuit being coupled to the pass transistor to generate the inhibitor signal in response to the pumped signal and the sensed signal.

### Claim 53

A method of operating an input buffer comprising:
receiving an input signal at an input node;
communicating the input signal to an input buffer circuit through an internal signal node;
controlling a pass transistor coupled between the input node and the internal signal node and a bias circuit coupled to the internal signal node with an inhibitor signal to activate the bias circuit to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node; and
providing the inhibitor signal from control circuitry.

### Claim 54 (depends on 53)

The method of claim 53 wherein controlling a pass transistor and a bias circuit further comprises deactivating the pass transistor and activating the bias circuit when the input signal reaches a predetermined threshold voltage level.

### Claim 55 (depends on 53)

The method of claim 53 wherein:
controlling a pass transistor further comprises controlling an n-channel transistor comprising a gate, a drain, and a source by coupling the inhibitor signal to the gate of the n-channel transistor; and
controlling a bias circuit further comprises controlling a pair of p-channel transistors and a resistor coupled in series between a voltage supply and the internal signal node by coupling the inhibitor signal to gates of each of the pair of p-channel transistors.

### Claim 56 (depends on 53)

The method of claim 53 wherein providing the inhibitor signal further comprises:
receiving a pumped signal and the input signal in a voltage sensor, and generating a sensed signal in the voltage sensor in response to the pumped signal and the input signal; and
receiving the pumped signal and the sensed signal in an inhibiting circuit, and generating the inhibitor signal in the inhibiting circuit in response to the pumped signal and the sensed signal.

### Claim 57

A method of operating an integrated circuit comprising:
receiving an input signal at an input node;
communicating the input signal to an input buffer circuit through an internal signal node;
controlling a pass transistor coupled between the input node and the internal signal node and a bias circuit coupled to the internal signal node with an inhibitor signal to activate the bias circuit to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node; and
providing the inhibitor signal from control circuitry to activate the pass transistor and deactivate the bias circuit while the input signal is less than a predetermined threshold voltage level, and to deactivate the pass transistor and activate the bias circuit when the input signal reaches the predetermined threshold voltage level.

### Claim 58 (depends on 57)

The method of claim 57 wherein:
controlling a pass transistor further comprises controlling an n-channel transistor comprising a gate, a drain, and a source by coupling the inhibitor signal to the gate of the n-channel transistor; and
controlling a bias circuit further comprises controlling a pair of p-channel transistors and a resistor coupled in series between a voltage supply and the internal signal node by coupling the inhibitor signal to gates of each of the pair of p-channel transistors.

### Claim 59 (depends on 57)

The method of claim 57 wherein providing the inhibitor signal further comprises:
receiving a pumped signal and the input signal in a voltage sensor, and generating a sensed signal in the voltage sensor in response to the pumped signal and the input signal; and
receiving the pumped signal and the sensed signal in an inhibiting circuit, and generating the inhibitor signal in the inhibiting circuit in response to the pumped signal and the sensed signal.

### Claim 60

A method of operating a memory device comprising:
receiving an input signal at an input node;
communicating the input signal to an input buffer circuit through an internal signal node;
controlling a pass transistor coupled between the input node and the internal signal node and a bias circuit coupled to the internal signal node with an inhibitor signal to activate the bias circuit to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node; and
providing the inhibitor signal from control circuitry to activate the pass transistor and deactivate the bias circuit while the memory device is in a non-test operation, and to deactivate the pass transistor and activate the bias circuit when the memory device is in a test mode indicated by an elevated voltage greater than a predetermined threshold voltage level provided on the input node.

### Claim 61 (depends on 60)

The method of claim 60 wherein:
controlling a pass transistor further comprises controlling an n-channel transistor comprising a gate, a drain, and a source by coupling the inhibitor signal to the gate of the n-channel transistor; and
controlling a bias circuit further comprises controlling a pair of p-channel transistors and a resistor coupled in series between a voltage supply and the internal signal node by coupling the inhibitor signal to gates of each of the pair of p-channel transistors.

### Claim 62 (depends on 60)

The method of claim 60 wherein providing the inhibitor signal further comprises:
receiving a pumped signal and the input signal in a voltage sensor, and generating a sensed signal in the voltage sensor in response to the pumped signal and the input signal; and
receiving the pumped signal and the sensed signal in an inhibiting circuit, and generating the inhibitor signal in the inhibiting circuit in response to the pumped signal and the sensed signal.

### Claim 63

An input system for a low-voltage flash memory device, comprising:
an input buffer comprising:
an input stage comprising a transistor comprising a gate, a drain, and a source, the gate being coupled to receive an inhibiting signal and the drain being coupled to receive an input signal, the transistor being controlled to inhibit the input signal from being presented at the source when the inhibiting signal is at a first predetermined level; and
an output stage coupled to the input stage to present the input signal to the low-voltage flash memory device; and
a voltage sensor coupled to receive the input signal and a pumped signal to trigger when the input signal is at a second predetermined level.

### Claim 64 (depends on 63)

The input system of claim 63 wherein:
the transistor comprises an n-channel transistor; and
the output stage comprises an inverter comprising a first connection and a second connection, the first connection being coupled to the source of the transistor and the second connection to present the input signal to the low-voltage flash memory device.

### Claim 65 (depends on 63)

The input system of claim 63 wherein the voltage sensor comprises a triggering stage comprising a set of p-channel transistors and a set of n-channel transistors coupled to receive to the input signal.

### Claim 66 (depends on 65)

The input system of claim 65 wherein the voltage sensor further comprises:
a set of metal options;
an inverting stage; and
a delay stage to reject undesired noise.

### Claim 67 (depends on 63)

The input system of claim 63, further comprising an inhibiting circuit coupled to receive the pumped signal and coupled to the voltage sensor to receive a sensed signal generated by the voltage sensor, the inhibiting circuit being coupled to the input buffer to generate the inhibiting signal in response to the pumped signal and the sensed signal.

### Claim 68

An input system for a low-voltage flash memory device, comprising:
an input buffer comprising:
an input stage comprising a transistor comprising a gate, a drain, and a source, the gate being coupled to receive an inhibiting signal and the drain being coupled to receive an input signal, the transistor being controlled to inhibit the input signal from being presented at the source when the inhibiting signal is at a first predetermined level; and
an output stage coupled to the input stage to present the input signal to the low-voltage flash memory device; and
an inhibiting circuit coupled to the input buffer to selectively produce the inhibiting signal, the inhibiting circuit being coupled to receive a pumped signal and a sensed signal.

### Claim 69 (depends on 68)

The input system of claim 68 wherein:
the transistor comprises an n-channel transistor; and
the output stage comprises an inverter comprising a first connection and a second connection, the first connection being coupled to the source of the transistor and the second connection to present the input signal to the low-voltage flash memory device.

### Claim 70 (depends on 68)

The input system of claim 68, wherein the inhibiting circuit comprises:
a first n-channel transistor comprising a gate coupled to receive the sensed signal, a drain coupled to present the inhibiting signal, and a source coupled to ground;
a second n-channel transistor comprising a gate coupled to an inverted sensed signal, a drain, and a source coupled to ground;
a first p-channel transistor comprising a gate coupled to the drain of the second n-channel transistor, a drain coupled to the drain of the first n-channel transistor, a source coupled to receive the pumped signal, and a bias coupled to receive the pumped signal; and
a second p-channel transistor comprising a gate coupled to the drain of the first n-channel transistor, a drain coupled to the drain of the second n-channel transistor, a source coupled to receive to the pumped signal, and a bias coupled to receive the pumped signal.

### Claim 71 (depends on 26)

The input system of claim 26, further comprising a voltage sensor coupled to receive the pumped signal and the input signal, the voltage sensor to generate the sensed signal, the inhibiting circuit being coupled to the voltage sensor to generate the inhibiting signal in response to the pumped signal and the sensed signal.