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AssigneeSTMicroelectronics S.r.l.
InventorsMarco Messina, Maurizio Perroni, Salvatore Polizzi
Estimating the term…
An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.
An electronic memory device monolithically integrated in a semiconductor and having an LPC (Low Pin Count) serial interface (2), of the type comprising a memory cell array (3) and associated row and column decode circuits;
A method of testing non-volatile memory devices having at least one LPC (Low Pin Count) serial communication interface and a conventional non-volatile memory cell array (3) and associated read, change, and erase circuits, characterized by:
Dependencies are inferred from the claim text.