Back to results
US 2004/0071026 A1Published application
Semiconductor integrated circuit device operating with low power consumption
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideto Hidaka
Life of this patent
Estimating the term…
Abstract
Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.
Claims34
A semiconductor device comprising:
- a first power source node;
- a logic gate including, as a component thereof, an insulated gate field effect transistor having a first gate tunnel barrier, for receiving a voltage on a first power source line as an operation power supply voltage and performing a predetermined operation;
- and
- a first switching transistor connected between said first power source node and said first power source line, formed of an insulated gate field effect transistor having a gate tunnel barrier larger than said first gate tunnel barrier, and selectively turned on in response to an operation mode instructing signal instructing an operation mode of said logic gate.
1 more element
A semiconductor device having a standby cycle and an active cycle, and receiving an input signal at a predetermined logical level in said standby cycle, said semiconductor device comprising:
- a first insulated gate field effect transistor having a first gate tunnel barrier, connected between a first power source node and a first output node, receiving said input signal on a gate thereof, and made conductive in said standby cycle;
- a second insulated gate field effect transistor having a gate tunnel barrier smaller than said first gate tunnel barrier, connected between said first output node and a second power source node, and receiving said input signal on a gate thereof to be made non-conductive in said standby cycle.
A semiconductor device having a standby cycle and an active cycle and receiving an input signal at a predetermined logical level in said standby cycle, comprising:
- a first insulated gate field effect transistor connected between a first power source node and a first output node, and receiving said input signal on a gate thereof;
- a second insulated gate field effect transistor connected between said first output node and a second power source node, and receiving said input signal on a gate thereof;
- and
- control circuitry coupled to the first and second insulated gate field effect transistors for reducing leak amounts of gate tunnel currents of said first and second insulated gate field effect transistors in said standby cycle below the leak amounts in said active cycle.
1 more element
A semiconductor device having a standby cycle and an active cycle and receiving an input signal of a predetermined logical level in said standby cycle, comprising:
- a first insulated gate field effect transistor connected between a first power source node and a first output node, receiving said input signal on a gate thereof, and having a first tunnel barrier;
- and
- a second insulated gate field effect transistor connected between said first output node and a sub-power source node, receiving said input signal on a gate thereof, and rendered conductive complementarily to said first insulated gate field effect transistor, said second insulated gate field effect transistor having a second gate tunnel barrier smaller than said first gate tunnel barrier;
- and
- a first switching transistor connected between said sub-power supply node and a second power source node, and selectively rendered conductive in response to an operation cycle instructing signal.
2 more elements
A semiconductor device comprising:
- a first power source node;
- a first power source line;
- a first switching transistor connected between said first power source node and said first power source line, and selectively made conductive in response to an operation cycle instructing signal;
- a first gate circuit receiving a voltage on said first power source line as an operation power supply voltage, said first gate circuit including an insulated gate field effect transistor as a component thereof;
- a second power source node;
- a second power source line separately arranged from said first power source line;
- a second switching transistor connected between said second power source node and said second power source line, and selectively rendered conductive in phase with said first switching transistor in response to said operation cycle instructing signal;
- and
- a second gate circuit receiving a voltage on said second power source line as an operation power supply voltage thereof, said second gate circuit including an insulated gate field effect transistor as a component thereof,
- a ratio between a size of a transistor of said first gate circuit connected to said first power source line and a size of said first switching transistor is substantially equal to a ratio between a size of a transistor of said second gate circuit connected to said second power source line and a size of said second switching transistor, with said size given by a ratio between a channel width and a channel length of an insulated field effect transistor.
7 more elements
A semiconductor device comprising:
- a precharge insulated gate field effect transistor for precharging a precharge node to a predetermined voltage in response to activation of a precharge instructing signal, said precharge insulated gate field effect transistor having a first gate tunnel barrier;
- and
- a gate circuit coupled to said precharge node, kept in a standby state during an active state of said precharge instructing signal, and driving said precharge node in accordance with an applied signal in an inactive state of said precharge instructing signal, said gate circuit including, as a component thereof, an insulated gate field effect transistor having a second gate tunnel barrier smaller than said first gate tunnel barrier.
A semiconductor device having a standby cycle and an active cycle, comprising:
- a precharge transistor being activated for a predetermined time upon transition from the standby cycle to the active cycle, for precharging a precharge node to a predetermined voltage;
- and
- a gate circuit for driving said precharge node in accordance with a signal applied in said active cycle, said gate circuit including, as a component thereof, an insulated gate field effect transistor having a first gate tunnel barrier same as said precharge transistor, and said first gate tunnel barrier being not greater than a gate tunnel barrier provided by a silicon oxide film of 3 nm (nanometer) in thickness.
A semiconductor device comprising:
- a normal array having a plurality of normal memory cells;
- a redundant array having spare memory cells for repairing a defective normal memory cell having a defect in said normal array;
- a normal access circuit for accessing a selected normal memory cell in said normal array, said normal access circuit including, as a component thereof, an insulated gate field effect transistor;
- a spare access circuit for accessing the spare memory cell in said redundant array, said spare access circuit including, as a component thereof, an insulated gate field effect transistor;
- and
- a power supply control circuit for setting a gate tunnel current of the insulated gate field effect transistor of an inactive circuit out of said spare access circuit and said normal access circuit to be smaller than the gate tunnel circuit of the transistor in an active circuit out of the spare and normal access circuits.
3 more elements
Dependencies are inferred from the claim text.