Flash memory device and fabricating method therefor
AssigneeAnam Semiconductor Inc.
InventorsTae Ho Choi, Jae Yeong Kim
Life of this patent
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Abstract
A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.
Claims17
A cell transistor for a flash memory device, comprising:
- a semiconductor substrate having a groove;
- a source region disposed in the semiconductor substrate, wherein the groove is recessed into an end portion of the source region;
- a drain region disposed in the semiconductor substrate to oppose the end portion of the source region;
- a gate insulating layer disposed on the substrate;
- and
- a floating gate, an inter-gate insulating layer, and a control gate sequentially disposed on the gate insulating layer, the floating gate overlapping with each opposing end portion of the source region and the drain region, wherein a portion of the floating gate protrudes to fill the groove in the source region.
A method of fabricating a cell transistor, comprising the steps of:
- forming a groove recessed into a semiconductor substrate;
- forming a source region in the semiconductor substrate, wherein the source region overlaps with the groove;
- sequentially forming a gate insulating layer, a floating gate, an inter-gate layer, and a control gate on the semiconductor substrate, wherein the floating gate fills the groove of the semiconductor substrate;
- and
- forming a drain region in the semiconductor substrate to thereby fabricate the cell transistor.
A transistor for a flash memory device, comprising:
- a semiconductor substrate;
- a source region and a drain region opposing each other in the semiconductor substrate;
- a floating gate disposed over the source and the drain region to overlap with opposing end portions thereof, wherein the floating gate has a tip protruding into the end portions of the source region;
- a gate insulating layer interposed between the semiconductor substrate and the floating gate;
- and
- an inter-gate insulating layer and a control gate sequentially disposed on the floating gate.
Dependencies are inferred from the claim text.