Circuit and method for implementing a write operation with tcct-based memory cells
AssigneeT-Ram, Inc.
InventorsSei-Seung Yoon, Seong-Ook Jung
Life of this patent
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Abstract
The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
Claims64
A memory device for storing one or more data bits, each of the one or more of the data bits is associated with a first logic state magnitude to represent a first logic state and a second logic state magnitude to represent a second logic state, the memory device comprising:
- a memory cell configured to store a first data bit;
- and
- a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude, the write access circuit configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
A write access circuit for programming a memory cell during a write operation, the write access circuit comprising:
- a transfer circuit configured to transfer a data bit during a first portion of the write operation;
- a driver register circuit configured to store the data bit and to drive a write data bit, and including an output, and an input coupled to the transfer circuit to receive the data bit;
- and
- an adjuster circuit coupled to the output of the driver register circuit, and is configured to adjust a characteristic of the write data bit during a second portion of the write operation.
A method for accessing a memory cell in performing a write operation, the method comprising:
- preparing a data bit for programming a memory cell, the data bit having a data bit magnitude associated with a first logic state magnitude to represent a first logic state and a second logic state magnitude to represent a second logic state;
- storing the data bit;
- translating the data bit magnitude to a write data bit magnitude, where the write data magnitude is used to program the data bit into the memory cell;
- and
- adjusting the write data bit magnitude associated with at least one of either the first logic state or the second logic state.
A computing device comprising:
- a central processing unit (CPU) configured to retrieve a data bit during a read operation and to provide the data bit during a write operation;
- and
- a memory device coupled to the CPU, where the memory device is configured to store the data bit, the memory device comprising
- a memory cell configured to store a stored data bit;
- a transfer circuit configured to transfer either the data bit or the stored data bit during a first portion of the write operation a data bit,
- a driver register circuit including an output, and an input coupled to the transfer circuit to receive either the data bit or the stored data bit, where the driver register circuit is configured to store either the data bit or the stored data bit and to drive a write data bit, and
- an adjuster circuit coupled to the output of the driver register circuit,
- where the adjuster circuit is configured to adjust a write data magnitude associated with the write data bit during a second portion of the write operation,
- the adjuster circuit further configured to apply the adjusted write data magnitude to the memory cell.
A memory device comprising:
- two or more thinly capacitively-coupled thyristor (TCCT) based memory cells connected to a word line two control line, where at least one of the two or more TCCT-based memory cell is selected to be programmed with a write data bit and at least another of the two or more TCCT-based memory cell is not selected to be programmed with the write data bit;
- a bit line coupled to the at least one TCCT-based memory cell;
- a TCCT-based reference memory cell configured to provide a reference signal;
- an input/output line;
- a cell select circuit coupled to the input/output line and configured to couple the bit line from the input/output line when the at least one TCCT-based memory cell is selected;
- a sense amplifier circuit having a first input and a second input configured to receive the reference signal, where the first input is coupled to the bit line and is configured to receive a data bit from the input/output line;
- and
- a write access circuit comprising
- a transfer circuit coupled to the first sense amplifier input and configured to transfer the data bit during a first portion of the write operation;
- a driver-register circuit including an input and an output, the input of the driver-register coupled to the transfer circuit to receive the data bit, where the driver-register circuit is configured to store the data bit and to drive the write data bit;
- and
- an adjuster circuit coupled to the output of the driver-register circuit, where the adjuster circuit is configured to adjust a write data bit magnitude as determined by a semiconductor device characteristic during a second portion of the write operation.
A memory device comprising:
- a memory cell configured to
- store a data bit capable of representing a logical one or a logical zero, and
- output a data signal with either
- a first magnitude to indicate that the data bit is the logical one, or
- a second magnitude to indicate that the data bit is the logical zero;
- and
- a write access circuit coupled to the memory cell and configured to provide a write signal to program the data bit into the memory cell, the write signal having either
- a third magnitude approximately equal to the first magnitude to program the memory cell with the data bit as the logical zero, or
- a fourth magnitude to program the memory cell the data bit as the logical one, the fourth magnitude being between the first and second magnitudes.
A memory device for accessing a memory cell in performing a write operation, the method comprising:
- means for preparing a data bit for programming a memory cell, the data bit having a data bit magnitude associated with a first logic state magnitude to represent a first logic state and a second logic state magnitude to represent a second logic state;
- means for storing the data bit;
- means for translating the data bit magnitude to a write data bit magnitude, where the write data magnitude is used to program the data bit into the memory cell;
- and
- means for adjusting the write data bit magnitude associated with at least one of either the first logic state or the second logic state.
Dependencies are inferred from the claim text.