Static random access memory
AssigneeIntel Corporation
InventorsLiqiong Wei, Kevin Zhang
Life of this patent
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Abstract
A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.
Claims31
An memory cell comprising:
- a pass transistor, a pull-down transistor, a first power supply, a second power supply, a precharge circuit, and a decoder circuit, each transistor having a threshold voltage, a gate and a channel, the channel having a first end and a second end, the second end of the channel of the pass transistor coupled to the first end of the channel of the pull-down transistor, and the second end of the channel of the pull-down transistor coupled to a ground connection, the first end of the channel of the pass transistor coupled to the first power supply via the precharge circuit and the gate of the pass transistor coupled to the second power supply via the decoder circuit, the first power supply and the second power supply each having a different power supply voltage.
A system comprising:
- a first power supply and a second power supply each power supply having a different power supply voltage;
- a processor;
- and
- a cache memory coupled to the processor, the cache memory comprising
- a plurality of pass transistors coupled to a corresponding plurality of pull-down transistors, the plurality of pull-down transistors coupled to a ground connection, each transistor in the plurality of pass transistors having a gate and a source, the source of each pass transistor is coupled to the first power supply via a precharge circuit and the gate of each pass transistor is coupled to the second power supply via a decoder circuit.
A method comprising:
- precharging at least one bitline coupled to a memory cell, the memory cell comprising at least one pass transistor, and at least one pull-down transistor, each transistor having a gate, a source, and a threshold voltage;
- and
- maintaining a value in the memory cell when the at least one pass transistor is in a standby mode by operating the at least one pass transistor in a sub-threshold region.
A 4-transistor static random access (SRAM) cell comprising:
- a first and a second pass transistor;
- a first pull-down transistor coupled to the first and second pass transistor;
- a second pull-down transistor coupled to the first and second pass transistor;
- a first power supply, having a first supply voltage, coupled to the first and the second pass transistor via a precharge circuit;
- and
- a second power supply having a different supply voltage compared with the first supply voltage, coupled to a gate of the first and second pass transistors via a decoder circuit.
An apparatus comprising:
- a bus interface unit;
- a core to process instructions;
- and
- a memory cell coupled to the bus interface unit and the core said memory cell comprising a pass transistor and a pull-down transistor, each transistor having a threshold voltage, a gate and a channel, the channel having a first end and a second end, the second end of the channel of the pass transistor coupled to the first end of the channel of the pull-down transistor, and the second end of the channel of the pull-down transistor coupled to a ground connection, the first end of the channel of the pass transistor coupled to a first power supply and the gate of the pass transistor coupled to a second power supply, the first power supply and the second power supply each having a different power supply voltage.
Dependencies are inferred from the claim text.