Multi-stage analog-to-digital converter with pipeline structure and method for coding the same

An analog-to-digital (“A/D”) converter comprising:

• a converter portion having at least three pipelined stages for receiving an analog input and generating a digital output;
• and
• an error correction portion in signal communication with the second of the at least three stages for correcting an error caused in the first of the at least three stages by updating an error correction bit.

A coding method of a multi-stage analog-to-digital (“A/D”) converter with pipeline structure comprising (a) a sample-and-hold unit for receiving, sampling and holding analog input signals, (b) a converter section having a plurality of stages for receiving an output of the sample-and-hold unit and generating digital data with a predetermined number of bits, and (c) a correction circuit for correcting an offset error by overlapping a least significant bit (“LSB”) of data of a previous stage and a most significant bit (“MSB”) of data of a subsequent stage when an offset error is caused in the previous stage, receiving the digital data from each stage of the converter section, and outputting digital output data, wherein a second stage of the converter section has an error correction bit in the digital data thereof for correcting an error caused in a first stage but a third and other stages coming after the third stage do not have an error correction bit.

A method of converting an analog input signal into a digital output signal, the method comprising:

• receiving an analog input signal;
• and
• providing at least one subsequent stage of a multi-stage pipelined structure for converting a portion of the received analog signal into a plurality of digital bits without an error bit.