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US 2004/0070442 A1Published application
Discrete-time analog filter
AssigneeIntel Corporation
InventorsJames E. Jaussi, Stephen R. Mooney
Life of this patent
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Abstract
A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.
Claims44
An analog filter comprising:
- a voltage-to-current converter to source a differential current;
- a current mirror coupled to the voltage-to-current converter to source a differential current proportional to the differential current sourced by the voltage-to-current converter;
- a current multiplier coupled to the current mirror to source a differential current proportional to the differential current sourced by the current mirror;
- and
- a differential latch coupled to the current multiplier to receive the differential current sourced by the current multiplier.
2 more elements
An analog filter comprising:
- a voltage-to-current converter comprising a first input port and a second input port, the voltage-to-current converter comprising:
- a first transistor comprising a gate connected to the first input port;
- and
- a second transistor comprising a gate connected to the second input port;
- wherein the first and second transistors source a differential current i;
- a current multiplier comprising a first output port and a second output port to shunt a weighted differential current (1−α)iCM so as to pass a weighted differential current αiCM to the first output port and the second output port, where α is a weight and where iCM is a differential current proportional to i.
3 more elements
A computer system comprising:
- a board comprising a first transmission line and a second transmission line;
- and
- a receiver coupled to the first and second transmission lines, the receiver comprising an analog filter, the analog filter comprising:
- a voltage-to-current converter comprising a first input port and a second input port, the voltage-to-current converter comprising:
- a first transistor comprising a gate connected to the first input port;
- and
- a second transistor comprising a gate connected to the second input port;
- wherein the first and second transistors source a differential current i;
- and
- a current multiplier comprising a first output port and a second output port to shunt a weighted differential current (1−α)iCM so as to pass a weighted differential current αiCM to the first output port and the second output port, where α is a weight and where iCM is a differential current proportional to i.
7 more elements
A voltage-to-current converter comprising:
- a first transistor to conduct a first current I1 and comprising a gate connected to the first input port;
- a second transistor to conduct a second current I2 and comprising a gate connected to the second input port;
- a third transistor coupled to the first transistor to conduct the first current I1;
- a fourth transistor coupled to the second transistor to conduct the second current I2;
- a current source to source a current I to the first and second transistors so that the sum of the first current I1 and the second current I2 is substantially equal to the current I;
- and
- a high-pass filter coupling the first input port and the second input port to the third and fourth transistors.
4 more elements
An analog filter comprising a set of taps, tap(i), i=1, 2, . . . , n, where for each i=1, 2, . . . , n, tap(i) comprises:
- a voltage-to-current converter(i) comprising a first input port(i) and a second input port(i), the voltage-to-current converter(i) comprising:
- a first transistor to conduct a first current I1(i) and comprising a gate connected to the first input port(i);
- a second transistor to conduct a second current I2(i) and comprising a gate connected to the second input port(i);
- a third transistor coupled to the first transistor to conduct the first current I1(i);
- a fourth transistor coupled to the second transistor to conduct the second current I2(i);
- a current source(i) to source a current I(i) to the first and second transistors so that the sum of the first current I1(i) and the second current I2(i) is substantially equal to the current I(i);
- and
- a high-pass filter coupling the first input port(i) and the second input port(i) to the third and fourth transistors;
- and
- a current multiplier(i) comprising a first output port(i) and a second output port(i), and coupled to the voltage-to-current converter(i) to shunt a current [1−α(i)]I1(i) so as to pass a first weighted current a(i)II(i) to the first output port(i) and to shunt a current [1−α(i)]I2(i) so as to pass a second weighted current α(i)I2(i) to the second output port(i), where α(i) is a weight.
7 more elements
A computer system comprising:
- a board comprising a first transmission line and a second transmission line;
- and
- a receiver coupled to the first and second transmission lines, the receiver comprising an analog filter, the analog filter comprising a set of taps, tap(i), i=1, 2, . . . , n, where for each i=1, 2, . . . , n, tap(i) comprises:
- a voltage-to-current converter(i) comprising a first input port(i) and a second input port(i), the voltage-to-current converter(i) comprising:
- a first transistor to conduct a first current I1(i) and comprising a gate connected to the first input port(i);
- a second transistor to conduct a second current I2(i) and comprising a gate connected to the second input port(i);
- a third transistor coupled to the first transistor to conduct the first current I1(i);
- a fourth transistor coupled to the second transistor to conduct the second current I2(i);
- a current source(i) to source a current I(i) to the first and second transistors so that the sum of the first current I1(i) and the second current I2(i) is substantially equal to the current I(i);
- and
- a high-pass filter(i) coupling the first input port(i) and the second input port(i) to the third and fourth transistors;
- and
- a current multiplier(i) comprising a first output port(i) and a second output port(i), and coupled to the voltage-to-current converter(i) to shunt a current [1−α(i)]I1(i) so as to pass a first weighted current α(i)I1(i) to the first output port(i) and to shunt a current [1−α(i)]I2(i) so as to pass a second weighted current α(i)I2(i) to the second output port(i), where α(i) is a weight.
10 more elements
An analog filter comprising a set of taps, tap(i), i=1, 2, . . . , n, where for each i=1, 2, . . . , n, tap(i) comprises:
- a voltage-to-current converter(i) comprising a first input port(i) and a second input port(i), the voltage-to-current converter(i) comprising:
- a first transistor to conduct a first current I1(i) and comprising a gate connected to the first input port(i);
- a second transistor to conduct a second current I2(i) and comprising a gate connected to the second input port(i);
- and
- a current source(i) to source a current I(i) to the first and second transistors so that the sum of the first current I1(i) and the second current I2(i) is substantially equal to the current I(i);
- an active current mirror(i) coupled to the voltage-to-current converter(i) to source currents I3(i) and I4(i), where I3(i)≡(IDC−ω(i)ΔI1(i)) and I4(i)=(IDC−ω(i)ΔI2(i)), where ω(i) is a weight, ΔI1 (i) is the differential of I1(i) with respect to its value when the first input port(i) and the second input port(i) are at a same voltage, and ΔI2(i) is the differential of I2(i) with respect to its value when the first input port(i) and the second input port(i) are at a same voltage, and IDC is a bias current;
- and
- a current multiplier(i) comprising a first output port(i) and a second output port(i), and coupled to the active current mirror(i) to shunt a current (1−α(i))I3(i) so as to pass a first weighted current α(i)I3(i) to the first output port(i) and to shunt a current (1−α(i))I4(i) so as to pass a second weighted current α(i)I4(i) to the second output port(i), where α(i) is a weight.
5 more elements
An analog filter comprising a set of taps, tap(i), i=1, 2, . . . , n, where for each i=1, 2, . . . , n, tap(i) comprises:
- a voltage-to-current converter(i) comprising a first input port(i) and a second input port(i), the voltage-to-current converter(i) comprising:
- a first transistor comprising a source, a drain, and a gate connected to the first input port(i);
- a second transistor comprising a source, a drain, and a gate connected to the second input port(i);
- and
- a current source(i) to source current to the first and second transistors;
- an active current mirror(i) comprising:
- a first transistor comprising a gate and a drain connected to the drain of the first transistor of the voltage-to-current converter(i);
- a second transistor comprising a gate and a drain connected to the drain of the second transistor of the voltage-to-current converter(i);
- a third transistor comprising a gate, a source connected to the drain of the first transistor of the active current mirror(i), and a drain;
- and
- a fourth transistor comprising a gate, a source connected to the drain of the second transistor of the active current mirror(i), and a drain;
- wherein the gates of the first, second, third, and fourth transistors of the active current mirror(i) are at a bias voltage;
- and
- a current multiplier(i) comprising a first output port(i) and a second output port(i), the current multiplier(i) comprising:
- a first set of parallel connected transistors, transistor(1,i,j), j=1, 2, . . . , k(i), where for each j=1, 2, . . . , k(i), transistor(1,i,j) comprises a source connected to the drain of the third transistor of the active current mirror(i), and a gate at a logical voltage D(i,j)*, where D(i,j)* denotes the Boolean complement of D(i,j);
- a second set of parallel connected transistors, transistor(2,i,j), j=1, 2, . . . , k(i), where for each j=1, 2, . . . , k(i), transistor(2,i,j) comprises a source connected to the drain of the third transistor of the active current mirror(i), a drain connected to the first output port(i), and a gate at the voltage D(i,j);
- a third set of parallel connected transistors, transistor(3,i,j), j=1, 2, . . . , k(i), where for each j=1, 2, . . . , k(i), transistor(3,i,j) comprises a source connected to the drain of the fourth transistor of the active current mirror(i), and a gate at the voltage D(i,j)*;
- and
- a fourth set of parallel connected transistors, transistor(4,i,j), j=1, 2, . . . , k(i), where for each j=1, 2, . . . , k(i), transistor(4,i,j) comprises a source connected to the drain of the fourth transistor of the active current mirror(i), a drain connected to the second output port(i), and a gate at the voltage D(i,j).
16 more elements
A computer system comprising:
- a board comprising a first transmission line and a second transmission line;
- and
- a receiver coupled to the first and second transmission lines, the receiver comprising an analog filter, the analog filter comprising a set of taps, tap(i), i=1, 2, . . . , n, where for each i=1, 2, . . . , n, tap(i) comprises:
- a voltage-to-current converter(i) comprising a first input port(i) and a second input port(i), the voltage-to-current converter(i) comprising:
- a first transistor to conduct a first current I1(i) and comprising a gate connected to the first input port(i);
- a second transistor to conduct a second current I2(i) and comprising a gate connected to the second input port(i);
- and
- a current source(i) to source a current I(i) to the first and second transistors so that the sum of the first current I1(i) and the second current I2(i) is substantially equal to the current I(i);
- an active current mirror(i) coupled to the voltage-to-current converter(i) to source currents I3(i) and I4(i), where I3(i)≡(IDC−ω(i)ΔI1(i)) and I4(i)=(IDC−ω(i)ΔI2(i)), where ω(i) is a weight, ΔI1 (i) is the differential of I1(i) with respect to its value when the first input port(i) and the second input port(i) are at a same voltage, and ΔI2(i) is the differential of I2(i) with respect to its value when the first input port(i) and the second input port(i) are at a same voltage, and IDC is a bias current;
- and
- a current multiplier(i) comprising a first output port(i) and a second output port(i), and coupled to the active current mirror(i) to shunt a current (1−α(i))I3(i) so as to pass a first weighted current α(i)I3(i) to the first output port(i) and to shunt a current (1−α(i))4(i) so as to pass a second weighted current (α(i)I4(i) to the second output port(i), where α(i) is a weight.
8 more elements
A computer system comprising:
- a board comprising a first transmission line and a second transmission line;
- and
- a receiver coupled to the first and second transmission lines, the receiver comprising an analog filter, the analog filter comprising a voltage-to-current converter, the voltage-to-current converter comprising:
- a first transistor to conduct a first current I1 and comprising a gate connected to the first input port;
- a second transistor to conduct a second current I2 and comprising a gate connected to the second input port;
- a third transistor coupled to the first transistor to conduct the first current I1;
- a fourth transistor coupled to the second transistor to conduct the second current I2;
- a current source to source a current I to the first and second transistors so that the sum of the first current I1 and the second current I2 is substantially equal to the current I;
- and
- a high-pass filter coupling the first input port and the second input port to the third and fourth transistors.
7 more elements
Dependencies are inferred from the claim text.