Delay adjustment circuit

A method for adjusting the delay of an internal clock of a semiconductor device, the method comprising:

• receiving a system clock signal and a feedback clock signal;
• generating a difference-pulse signal that indicates a phase difference between the system clock signal and the feedback clock signal;
• generating an interim clock signal that is selected from the group comprising the feedback clock signal and an inversion of the feedback clock signal;
• generating a plurality of output signals that indicate the phase difference between the system clock signal and the interim clock signal;
• delaying the interim clock signal by an amount of time that is a function of the phase difference indicated by the plurality of output signals to produce a delayed interim clock signal;
• and
• providing the delayed interim clock signal as an internal clock signal.

A delay adjustment circuit for a semiconductor device, comprising:

• a means for receiving a system clock signal and a feedback clock signal and generating a difference-pulse signal that indicates a phase difference between the system clock signal and the feedback clock signal;
• a means for generating an interim clock signal that is selected from the group comprising the feedback clock signal and an inversion of the feedback clock signal;
• a means for generating a plurality of output signals that indicate the phase difference between the system clock signal and the interim clock signal;
• and
• a means for delaying the interim clock signal by an amount of time that is a function of the phase difference indicated by the plurality of output signals to produce a delayed interim clock signal, and providing the delayed interim clock signal as an internal clock signal.