US 2004/0070436 A1Published application

PWM control circuit, microcomputer and electronic equipment

AssigneeSeiko Epson Corporation

InventorsMakoto Kudo, Katsuya Iida

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Abstract

A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by ½, ¼, {fraction (2/4)} or ¾ clock period.

Claims15

Dependent claims

A PWM (pulse width modulation) control circuit for generating a PWM signal, comprising:

a counter for incrementing or decrementing a count value in accordance with a given operation clock;
an edge-point value setting register for storing an edge-point value which specifies a first edge-point at which the level of the PWM signal varies;
a PWM output circuit for varying the level of the PWM signal at said first edge-point specified by said edge-point value, based on said count value from said counter and said edge-point value from said edge-point value setting register;
a delay value setting register provided on low order side of said edge-point value setting register, for storing a delay value of at least one bit which specifies a delay time of said first edge-point;
and
a period value setting register for storing a period value which specifies a period of the PWM signal,
wherein said PWM output circuit delays said first edge-point by a period which is smaller than one-clock period of said operation clock, in accordance with said delay value stored in said delay value setting register.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/681,302Filed 9 Oct 2003
Priority: JP 11-06970916 Mar 1999
Published: 15 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 7/08
Modulating pulses with a continuously-variable modulating signal: duration or width modulation ; Duty cycle modulation
G06F 1/025
Digital function generators: for functions having two-valued amplitude, e.g. Walsh functions
H03K
Pulse technique
G06F
Computing and data processing

Family

Application09/525,261Continuation · filed 14 Mar 2000
Application10/681,302Continuation · filed 9 Oct 2003
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From the US filing history. Foreign family members aren’t listed.