Duty ratio detecting apparatus with small return time

A duty ratio correcting apparatus for receiving and correcting an external clock signal, comprising:

• a duty ratio adjusting circuit for receiving said external clock signal and adjusting a duty ratio of said external clock signal to generate an internal clock signal;
• a differentializing circuit, connected to said duty ratio adjusting circuit, for differentializing said internal clock signal to generate first and second complementary duty ratio signals;
• a duty ratio detecting circuit, connected to said differentializing circuit, for detecting first and second duty ratios of said first and second complementary duty ratio signals;
• a switch circuit connected to said duty ratio detecting circuit;
• and
• a duty ratio maintaining circuit, connected between said switch circuit and said duty ratio adjusting circuit, for maintaining said first and second duty ratios via said switch circuit as third and fourth duty ratios, respectively, so that said duty ratio adjusting circuit adjusts the duty ratio of said external clock signal in accordance with said third and fourth duty ratios,
• said duty ratio adjusting circuit and said differentializing circuit being deactivated by receiving a stand-by signal, said switch being opened by receiving said stand-by signal,
• said duty ratio detecting circuit comprising:
• first and second nodes;
• a load current supplying circuit for supplying first and second load currents to said first and second nodes, respectively;
• and
• a current switch connected to said first and second nodes, said current switch operating in response to first and second complementary duty ratio signals,
• said duty ratio maintaining circuit comprising third and fourth nodes for receiving and maintaining said first and second duty ratios at said first and second nodes, respectively,
• said switch circuit comprising:
• a first switch connected between said first and third nodes;
• and
• a second switch connected between said second and fourth nodes,
• said load current supplying circuit being controlled by said third and fourth duty ratios at said third and fourth nodes, respectively.