Circuit and method for generating a local clock signal
AssigneeAgere Systems Inc.
InventorLindor E. Henrickson
Life of this patent
Estimating the term…
Abstract
A circuit and method for generating a local clock signal and a telecommunications system incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a phase detector for receiving an input data signal, (2) (at least) first and second continuously controllable delay lines, coupled to the phase detector, for producing respective first and second candidate local clock signals and (3) delay line selector, coupled to the first and second delay lines, for selecting one of the first and second candidate local clock signals to be the local clock signal based on phase excursions in the input data signal.
Claims21
A circuit for generating a local clock signal, comprising:
- a phase detector for receiving an input data signal;
- first and second continuously controllable delay lines, coupled to said phase detector, for producing respective first and second candidate local clock signals;
- and
- delay line selector, coupled to said first and second delay lines, for selecting one of said first and second candidate local clock signals to be said local clock signal based on phase excursions in said input data signal.
A method of generating a local clock signal, comprising:
- detecting a phase of an input data signal;
- employing first and second continuously controllable delay lines to produce respective first and second candidate local clock signals;
- and
- selecting one of said first and second candidate local clock signals to be said local clock signal based on phase excursions in said input data signal.
A synchronous telecommunications system, comprising:
- circuitry for receiving an input data signal from a remote source, said input data signal subject to excess jitter;
- a phase detector for detecting a phase of said input data signal;
- first and second continuously controllable delay lines, coupled to said phase detector, for producing respective first and second candidate local clock signals;
- delay line selector, coupled to said first and second delay lines, for selecting one of said first and second candidate local clock signals to be said local clock signal based on phase excursions in said input data signal, said phase detector comparing a phase of said local clock signal to said phase of said input data signal to yield a phase offset signal indicating said phase excursions, said local clock signal having less of said jitter;
- and
- data processing circuitry for processing said input data signal based on said local clock signal.
Dependencies are inferred from the claim text.