Programmable logic devices having enhanced cascade functions to provide increased flexibility
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsSushma Mohan, Parvesh Swami
Life of this patent
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Abstract
A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBS) providing enhanced flexibility for Cascade logic functions, each comprising a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions. The other input of the Cascade Logic block is a Cascade-In signal. A 2-input selection multiplexer receives one input from the output of the Cascade Logic block and the other from the output of the LUT for selecting either the Cascade Logic output or the LUT output as the unregistered output. The arrangement is such that the Cascade output and the multiplexer output are simultaneously available from the PLB.
Claims27
A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBS) providing enhanced flexibility for Cascade logic functions, each comprising:
- a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions receiving a Cascade-In input as the other input, and
- a 2-input selection multiplexer receiving one input from the output of the Cascade Logic block and the other from the output of the LUT for selecting either the Cascade Logic output or the LUT output as the unregistered output,
- the arrangement being such that the output of the cascade logic and the unregistered output are simultaneously available, as separate outputs of the PLB
A method for enhancing the flexibility of Cascade Logic functions in the Programmable logic Block (PLB) of a Programmable Logic Device (PLD), comprising the steps of:
- providing a 2-input selection multiplexer for receiving one input from the output of the Cascade Logic block and the other from the output of the LUT and selecting either the Cascade Logic output or the LUT output as the unregistered output, and
- providing simultaneous access to the cascade logic output and the unregistered output as separate outputs of the PLB for use as sub functions in cascade logic or in other logic functions.
A programmable logic block, comprising:
- a logic array operable to generate a first signal;
- a first cascade logic circuit coupled to the array and operable to receive a second signal from a second cascade logic circuit of another programmable logic block and to generate a third signal from the first and second signals;
- and
- a first multiplexer operable to receive the first and third signals and a first control signal and to pass either the first or third signal in response to the control signal.
An integrated circuit, comprising:
- a first programmable logic block having a first cascade logic circuit operable to generate a first signal;
- and
- a second programmable logic block comprising,
- a logic array operable to generate a second signal,
- a second cascade logic circuit coupled to the first programmable logic block and to the logic array and operable to generate a third signal from the first and second signals, and
- a multiplexer operable to receive the second and third signals and a control signal and to pass either the second or third signal in response to the control signal.
An electronic system, comprising:
- an integrated circuit, comprising,
- a first programmable logic block having a first cascade logic circuit operable to generate a first signal, and
- a second programmable logic block comprising,
- a logic array operable to generate a second signal,
- a second cascade logic circuit coupled to the first programmable logic block and to the logic array and operable to generate a third signal from the first and second signals, and
- a multiplexer operable to receive the second and third signals and a control signal and to pass either the second or third signal in response to the control signal.
A method, comprising:
- generating a first signal with a first cascade logic circuit of a first programmable logic block;
- generating a second signal with a logic array of a second programmable logic block;
- generating from the first and second signals a third signal with a second cascade logic circuit of the second programmable logic block;
- and
- selectively passing either the second or third signal to an output node of the second programmable logic block.
A method, comprising:
- generating a first signal with a first cascade logic circuit of a first programmable logic block;
- passing a second signal that is selectively equal to either the first signal or a complement of the first signal to a second cascade logic circuit of a second programmable logic block;
- generating a third signal with a logic array of the second programmable logic block;
- generating from the second and third signals a fourth signal with the second cascade logic circuit;
- and
- selectively passing either the third or fourth signal to an output node of the second programmable logic block.
A method, comprising:
- generating a first signal with a first cascade logic circuit of a first programmable logic block;
- generating a second signal with a logic array of a second programmable logic block;
- generating from the first and second signals a third signal with a second cascade logic circuit of the second programmable logic block;
- selectively passing either the second or third signal;
- and
- registering the passed signal.
Dependencies are inferred from the claim text.