Semiconductor package with enhanced chip groundability and method of fabricating the same

A semiconductor package method, comprising the steps of:

• preparing a wafer, which is partitioned by a number of predefined singulation lines into a plurality of chips, wherein each of the chips has an active surface formed with a plurality of ground pads and the ground pads on any two adjacent chips disposed across one of the singulation lines are interconnected by a plurality of elongated portions.
• forming a plurality of trenches along the singulation lines on the wafer;
• performing a filling process to fill the trenches with the electrically conductive material being in electrical contact with the elongated portions of the ground pads;
• singulating the wafer along the singulation lines into the electrically-conductive material in the trenches so as to separate each of the chips from the wafer and meanwhile form an electrically-conductive wall attached to the sidewalls of each of the chips;
• performing a die-mounting process to mount at least one of the singulated chips on a front surface of a substrate by means of an electrically-conductive adhesive on the substrate, with the electrically-conductive adhesive being in electrical contact with both the electrically-conductive wall on the sidewall of the chip and a grounding plane on the substrate, so as to electrically connect each ground pad on the chip to the grounding plane on the substrate;
• performing a molding process to form an encapsulation body over front surface of the substrate for encapsulating the chip;
• and
• performing a ball-implantation process to implant a plurality of solder balls on the ground-ball pads over a back surface of the substrate, allowing the ground pads on the chip to be electrically connected to an external device via the solder balls implanted on the ground-ball pads on the substrate.

A semiconductor packaging method, comprising the steps of:

• preparing a wafer, which is partitioned by a number of predefined singulation lines into a plurality of chips, wherein each of the chips has an active surface formed with a plurality of ground pads and the ground pads on any two adjacent chips disposed across one of the singulation lines are interconnected by a plurality of elongated portions.
• forming a plurality of trenches along the singulation lines on the wafer;
• performing a filling process to fill the trenches with the electrically conductive material being in electrical contact with the elongated portions of the ground pads;
• singulating the wafer along the singulation lines into the electrically-conductive material in the trenches so as to separate each of the chips from the wafer and meanwhile form an electrically-conductive wall attached to the sidewalls of each of the chips;
• performing a disposing process to dispose a curable electrically-conductive material into the trenches, and then baking the curable electrically-conductive material in the trenches, so as to allow the curable electrically-conductive material to come into electrical contact with the elongated portions of the ground pads;
• performing a die-mounting process to mount at least one of the singulated chips on a front surface of a substrate by means of an electrically-conductive adhesive on the substrate, with the electrically-conductive adhesive being in electrical contact with both the electrically-conductive wall on the sidewall of the chip and a grounding plane on the substrate, so as to electrically connect each ground pad on the chip to the grounding plane on the substrate;
• performing a molding process to form an encapsulation body over front surface of the substrate for encapsulating the chip;
• and
• performing a ball-implantation process to implant a plurality of solder balls on the ground-ball pads over a back surface of the substrate, allowing the ground pads on the chip to be electrically connected to an external device via the solder balls implanted on the ground-ball pads on the substrate.