Semiconductor device with resistor pattern and method of fabricating the same

A method of fabricating a semiconductor device comprising:

• forming a device isolation layer in a substrate to define an active region;
• forming a gate pattern and a resistor pattern that include sequentially stacked first and second conductive layers on the active region and the device isolation layer, respectively;
• forming gate spacers and resistor spacers on sidewalls of the gate pattern and the resistor pattern, respectively;
• removing the second conductive layer of the resistor pattern to expose a portion of the inner sidewalls of the resistor spacers and a of the first conductive layer;
• and
• forming resistor electrodes connected to ends of the resistor pattern.

A method of fabricating a semiconductor substrate comprising:

• forming a device isolation layer in a substrate to define an active region;
• stacking a polysilicon layer and a silicide layer on the entire surface of the substrate;
• patterning the polysilicon layer and the silicide layer to form a gate pattern of a first polysilicon pattern and a first silicide pattern on the active region, and to form a line-shaped resistor pattern of a second polysilicon pattern and a second silicide pattern on the device isolation layer;
• forming gate spacers and resistor spacers on sidewalls of the gate pattern and the resistor pattern, respectively;
• etching the second silicide pattern to expose a portion of inner sidewalls of the resistor spacers aligned to sidewalls of the second polysilicon pattern and a top of the second polysilicon pattern;
• and
• forming resistor electrodes connected to ends of the resistor pattern, respectively.

A method of fabricating a semiconductor device comprising:

• forming a device isolation layer in a substrate to define an active region;
• stacking a polysilicon layer and a silicide layer on an entire surface of the substrate;
• patterning the polysilicon layer and the silicide layer to form a gate pattern comprising a first polysilicon pattern and a first silicide pattern on the active region, and to form a line-shaped resistor pattern comprising a second polysilicon pattern and a second silicide pattern on the device isolation layer;
• forming gate spacers and resistor spacers on sidewalls of the gate pattern and the resistor pattern, respectively;
• etching the second silicide pattern of the resistor pattern to expose a portion of the inner sidewalls of the resistor pattern aligned to sidewalls of the second polysilicon pattern and a top of the second polysilicon pattern;
• forming upper spacers including a vertical sidewall aligned to the inner sidewall of the resistor spacers and a curved sidewall opposite to the vertical sidewall, on the inner sidewalls of the exposed resistor spacers on the exposed second polysilicon pattern;
• using the upper spacers as an etch mask, etching the second polysilicon pattern to form a hollow region where the device isolation layer is exposed, wherein the hollow region includes sidewalls aligned to the curved sidewalls of the upper spacers;
• and
• forming resistor electrodes connected to both edges of the resistor pattern.