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US 2004/0070025 A1Published application
NROM memory cell
OwnerBoaz Eitan, Elard Stein Von Kamienski +2inventors
InventorsBoaz Eitan, Elard Stein Von Kamienski, Stephan Riedel, Assaf Shappir
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Abstract
An NROM memory cell is of a planar configuration without an additional oxidation being affected for the fabrication of the bit line oxide. The ONO layer is provided as a memory layer and is disposed with a uniform thickness on the semiconductor material of the source and drain regions and of the channel region, so that the ONO layer forms not only the gate dielectric, but also the insulation of the bit lines from the word lines or the gate electrode.
Claims4
An NROM memory cell, comprising:
- a semiconductor body;
- doped regions for a source and a drain formed on said semiconductor body and disposed at a distance from one another;
- a channel region defined in said semiconductor body and disposed between said doped regions;
- a gate electrode disposed above said channel region between said doped regions;
- and
- a memory layer provided as a gate dielectric and as a memory medium, said memory layer disposed between said gate electrode and said channel region, said memory layer having an oxide-nitride-oxide layer sequence and
- a bit line oxide for electrically insulating said doped regions from said gate electrode, said memory layer disposed above said channel region and above said doped regions with a uniform thickness.
4 more elements
Dependencies are inferred from the claim text.