# US 2004/0070018 A1 · Semiconductor memory circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2004/0070018 A1 - Document ID: US20040070018A1 - Status: Published application - Kind: A1 - Application number: 08/530,661 - Filed: 1995-09-20 - Published: 2004-04-15 - Earliest claimed: 1995-09-20 - Assignees: Micron Technology, Inc. - Inventors: BRENT KEETH; PIERRE C. FAZAN - Web page: https://patentgrep.com/patent/US20040070018A1 ## CPC - H10B 12/485: {Bit line contacts} - H10B 12/00: Dynamic random access memory [DRAM] devices - H10B 12/312: {with a bit line higher than the capacitor} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells. ## Claims ### Claim 1 (Withdrawn) A 64 M semiconductor memory device comprising: a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body; a total of from 64,000,000 to 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die the individual functional and operably addressable memory cells occupying area on the die within the memory arrays, the occupied area of all functional and addressable memory cells on the die having a total combined area which is no greater than 53 mm2; and peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays; the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays. ### Claim 2 (depends on 1) (Withdrawn) The semiconductor memory device of claim 1 wherein the die is fabricated to include a total of four or less composite conductive line layers. ### Claim 3 (depends on 1) (Withdrawn) The semiconductor memory device of claim 1 wherein the peripheral circuitry, the pitch circuitry and the memory arrays have a total combined continuous surface area on the die which is less than or equal to 106 mm2. ### Claim 4 (depends on 1) (Withdrawn) The semiconductor memory device of claim 1 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include at least five composite conductive line layers, the occupied area of all functional and operable memory cells on the die having a total combined area on the die which is no greater than 40 mm2. ### Claim 5 (depends on 1) (Withdrawn) The semiconductor memory device of claim 1 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include at least five composite conductive line layers; the peripheral circuitry, the pitch circuitry and the memory arrays having a total combined continuous surface area on the die which is less than or equal to 93 mm2. ### Claim 6 (Currently amended) A semiconductor device including a memory, the semiconductor device comprising: a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body; a total of from at least 16,000,000 to 17,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the semiconductor die, the individual functional and operably addressable memory cells occupying area on the semiconductor die within the memory arrays, the occupied area of all functional and addressable memory cells on the semiconductor die having a total combined area which is no greater than 14 mm2; and peripheral circuitry and pitch circuitry formed on the semiconductor die relative to the memory arrays; the peripheral circuitry electrically interconnecting with the interconnect pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays. ### Claim 7 (depends on 6) (Previously presented) The semiconductor device of claim 6 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include a total of four or less conductive line layers. ### Claim 8 (depends on 6) (Currently amended) The semiconductor device of claim 6 wherein the peripheral circuitry, the pitch circuitry and the memory arrays have a total combined continuous surface area on the semiconductor die which is less than or equal to 35 mm2. ### Claim 9 (depends on 6) (Currently amended) The semiconductor device of claim 6 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include at least five conductive line layers, the occupied area of all functional and operable memory cells on the semiconductor die having a total combined area on the die which is no greater than 11 mm2. ### Claim 10 (depends on 6) (Currently amended) The semiconductor device of claim 6 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include at least five conductive line layers; the peripheral circuitry, the pitch circuitry and the memory arrays having a total combined continuous surface area on the semiconductor die which is less than or equal to 32 mm2. ### Claim 11 (Withdrawn) A 4 M semiconductor memory device comprising: a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body; a total of from 4,000,000 to 4,500,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die, the individual functional and operably addressable memory cells occupying area on the die within the memory arrays, the occupied area of all functional and addressable memory cells on the die having a total combined area which is no greater than 3.3 mm2; and peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays; the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays. ### Claim 12 (depends on 11) (Withdrawn) The semiconductor memory device of claim 11 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include a total of four or less composite conductive line layers. ### Claim 13 (depends on 11) (Withdrawn) The semiconductor memory device of claim 11 wherein the peripheral circuitry, the pitch circuitry and the memory arrays have a total combined continuous surface area on the die which is less than or equal to 11.0 mm2. ### Claim 14 (depends on 11) (Withdrawn) The semiconductor memory device of claim 11 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include at least five composite conductive line layers, the occupied area of all functional and operable memory cells on the die having a total combined area on the die which is no greater than 2.5 mm2. ### Claim 15 (depends on 11) (Withdrawn) The semiconductor memory device of claim 11 wherein the peripheral circuitry, the pitch circuitry, and the memory arrays are fabricated to include at least five composite conductive line layers; the peripheral circuitry, the pitch circuitry and the memory arrays having a total combined continuous surface area on the die which is less than or equal to 10.2 mm2. ### Claim 16 (Withdrawn) A 64 M semiconductor memory device comprising: a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body; a total of from 64,000,000 to 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells; and peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays; the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays. ### Claim 17 (depends on 16) (Withdrawn) The semiconductor memory device of claim 16 wherein at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells. ### Claim 18 (Currently amended) A semiconductor device including a memory, the semiconductor device comprising: a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body; a total of from at least 16,000,000 to 17,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the semiconductor die, at least one of the memory arrays containing at least one area of 100 square microns of continuous semiconductor die surface area having at least 128 of the functional and operably addressable memory cells; and peripheral circuitry and pitch circuitry formed on the semiconductor die relative to the memory arrays; the peripheral circuitry electrically interconnecting with the interconnect pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays. ### Claim 19 (depends on 18) (Currently amended) The semiconductor device of claim 18 wherein the at least one of the memory arrays containing at least one area of 100 square microns of continuous semiconductor die surface area has at least 170 of the functional and operably addressable memory cells. ### Claim 20 (Withdrawn) A 4 M semiconductor memory device comprising: a semiconductor die encapsulated in a package, the package having an encapsulating body and electrically conductive interconnect pins extending outwardly from the body; a total of from 4,000,000 to 4,500,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on the die, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells; and peripheral circuitry and pitch circuitry formed on the die relative to the memory arrays; the peripheral circuitry electrically interconnecting with the pins and including operably interconnected control and timing circuitry, address and redundancy circuitry, data and test path circuitry, and voltage supply circuitry which collectively enable full access to all addressable memory cells of the memory arrays. ### Claim 21 (depends on 20) (Withdrawn) The semiconductor memory device of claim 20 wherein at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells. ### Claim 22 (Currently amended) A semiconductor device including a memory, the semiconductor device comprising: a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the functional and operably addressable memory cells, at least one of the memory arrays containing at least one area of 100 square microns of continuous semiconductor die surface area having at least 128 of the functional and operably addressable memory cells. ### Claim 23 (depends on 22) (Currently amended) The semiconductor device of claim 22 wherein the a total number of functional and operably addressable memory cells on the semiconductor die is no more than 17,000,000. ### Claim 24 (depends on 22) (Withdrawn) The semiconductor memory device of claim 22 wherein the total number of functional and operably addressable memory cells on the semiconductor die is no more than 4,500,000. ### Claim 25 (depends on 22) (Currently amended) The semiconductor device of claim 22 wherein the at least one of the memory arrays containing at least one area of 100 square microns of continuous semiconductor die surface area has at least 170 of the functional and operably addressable memory cells. ### Claim 26 (depends on 22) (Currently amended) The semiconductor device of claim 22 wherein the at least one of the memory arrays containing at least one area of 100 square microns of continuous semiconductor die surface area has at least 170 of the functional and operably addressable memory cells, and the a total number of functional and operably addressable memory cells on the semiconductor die is no more than 17,000,000. ### Claim 27 (depends on 22) (Withdrawn) The semiconductor memory device of claim 22 wherein at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells, and the total number of functional and operably addressable memory cells on the semiconductor die is no more than 4,500,000.