Methods of forming semiconductor constructions

A semiconductor construction comprising:

• a field effect transistor having an access side and an opposing bitline side;
• a pair of source/drain regions associated with the field effect transistor;
• one of the source/drain regions being on the access side and the other source/drain region being on the bitline side of the field effect transistor device;
• and
• an indium implant associated with only one of the pair of source/drain regions.

A semiconductor construction comprising:

• a semiconductor substrate
• a pair of conductively doped diffusion regions within a semiconductive material of the substrate, the conductively doped diffusion regions comprising a first type of dopant;
• a transistor construction over the substrate, the transistor construction comprising:
• a gate disposed between the pair of diffusion regions and having a pair of opposing sidewalls;
• spacers disposed along the opposing sidewalls, the conductively doped diffusion regions extending under the spacers;
• and
• a diffusion region extension present on a first side of the transistor construction and absent on an opposing second side of the transistor construction, the diffusion region extension comprising a second type of dopant and extending the diffusion region farther beneath the transistor construction on the first side of the transistor construction relative to the diffusion region on the second side of the transistor construction.

A semiconductor construction comprising:

• a semiconductive material substrate;
• a first and a second transistor construction over the semiconductive substrate material, each of the first and second transistor constructions having opposing sidewalls with a pair of insulative spacers along the sidewalls;
• a first and a second source/drain region within the substrate, the first transistor construction being disposed between the first and the second source/drain regions, a first end of the first source/drain region extending beneath the spacer on a first side of the first transistor construction and the second source/drain region extending beneath the spacer on an opposing second side of the first transistor construction;
• a third and a fourth source/drain region within the substrate, the second transistor construction being disposed between the third and fourth source/drain regions, a first side of the fourth source/drain region extending beneath the spacer on a first side of the second transistor construction, and the third source/drain region extending beneath the spacer on an opposing second side of the second transistor construction;
• the first, second, third and fourth source/drain regions being commonly doped with a first type of dopant;
• a source/drain extension associated with the first side of the first source/drain region, the source/drain extension being doped with a second type of dopant and extending the first side of the first source/drain region farther beneath the first transistor construction;
• extensions being absent from a second side of the first source/drain region, and absent from the second source/drain region.

A DRAM construction comprising:

• a first and a second gate structure;
• four nodes, the four nodes comprising a first node, a second node, a third node and a fourth node, the first node being in gated electrical connection with the second node through the first gate structure, and the third node location being in gated electrical connection with the fourth node location through the second gate structure;
• each of the four nodes having a diffusion region associated therewith, the diffusion regions associated with the first and second nodes each extending under the first gate structure, and the diffusion regions associated with the third and fourth nodes extending under the second gate structure;
• an isolation region between the second and third nodes, the isolation region electrically isolating the first and the second gate structures from one another;
• a bit line contact in electrical connection with the first node;
• a capacitor construction in electrical connection with the second node, the capacitor construction comprising a storage node;
• an indium implant in the diffusion region associated with the first node, the implant being under the first gate structure proximate the first node;
• and
• an absence of an indium implant in the diffusion region associated with the second node.

A method of forming a doped region in a semiconductor substrate comprising:

• forming a pair of blocks over a semiconductive material of a semiconductor substrate, the pair of blocks being spaced from each other by a gap comprising a first distance;
• narrowing the gap;
• and
• implanting dopant into the semiconductive material though the narrowed gap to form a doped region in the semiconductive material.

A method of forming a semiconductor construction, comprising:

• forming a layer of patternable material over a semiconductive substrate material;
• patterning the layer of patternable material to form at least two patterned blocks, a pair of adjacent blocks being separated by a first gap;
• forming a coating over the pair of adjacent blocks and across the first gap between the adjacent blocks;
• selectively removing the coating from across the first gap while leaving the coating on the pair of adjacent blocks;
• the pair of blocks and coating together defining a pair of enlarged blocks that are separated by a second gap;
• the second gap being narrower than the first gap;
• while the enlarged blocks remain over the semiconductive substrate material, implanting at least one dopant within the semiconductive material within the second gap to form a doped region;
• and
• removing the enlarged blocks from over the semiconductive substrate material.

A DRAM forming method comprising:

• forming a first wordline and a second wordline over a substrate, each wordline comprising a pair of opposing sidewalls;
• defining four nodes proximate the wordlines, the four nodes comprising a first node, second node, third node and fourth node, the second node being in gated electrical connection with the first node through the first wordline, and the fourth node being in gated electrical connection with the third node through the second wordline;
• defining a first, second, third and fourth diffusion regions, the first diffusion region being associated with the first node, the second diffusion region being associated with the second node, the third diffusion region being associated with the third node, and the fourth diffusion region being associated with the fourth node;
• defining an isolation region between the first wordline and the second wordline, the isolation region electrically isolating the first and second wordlines from each other;
• forming a pair of spacers along opposing sidewalls of each wordline;
• the first and second diffusion regions extending an initial distance under the first wordline, and the third and fourth diffusion regions extending an initial distance under the second wordline;
• and
• extending the first diffusion region farther under the first wordline relative to the initial distance without extending the second diffusion region.

A method of forming a semiconductor construction, comprising:

• forming a dielectric material over a semiconductive substrate material;
• patterning the dielectric material to form at least two patterned blocks, a pair of adjacent blocks being separated by a first gap, each block having a sidewall within the first gap;
• forming a pair of spacers along the sidewalls and within the first gap, the spacers having lateral edges separated by a gap, the second gap being narrower than the first gap;
• while the spacers remain along the sidewalls, implanting at least one dopant into the semiconductive material within the second gap to form a doped region;
• and
• removing the spacers from along the sidewalls.