Photo imager with shared reset FET and pixel amplifier
AssigneeSilicon Video Corporation
InventorsJeffrey J. Zarnowski, Samuel D. Ambalayanar, Michael E. Joyner, Ketan V. Karia
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AssigneeSilicon Video Corporation
InventorsJeffrey J. Zarnowski, Samuel D. Ambalayanar, Michael E. Joyner, Ketan V. Karia
Estimating the term…
A solid state imager with pixels arranged in columns and rows has the pixels are configured into groups of at least a first pixel and a second pixel, each said group sharing a pixel output transistor having a sense electrode and an output electrode and a reset transistor having a gate coupled to receive a reset signal and an output coupled to the sense electrode of the associated shared pixel output transistor. Each of the pixels has a photosensitive element whose output electrode is coupled to the sense electrode of the shared pixel output transistor and a gate electrode coupled to receive respective first and second pixel gating signals. This configuration reduces the number of FETs to two transistors for each pair of pixels, and also can achieve true correlated double sampling correction of FPN.
A photosensitive array comprised of a plurality of pixels arranged in columns and rows, wherein the pixels are configured such that each said pixel has two transistors;
A photosensitive array comprised of a plurality of pixels arranged in columns and rows, wherein the pixels are configured into groups of at least a first pixel and a second pixel, each said group including
Dependencies are inferred from the claim text.