Design techniques enabling storing of bit values which can change when the design changes

A method of allowing the value of a bit stored in integrated circuits to be changed when the design of integrated circuits changes, said method comprising:

• providing in a first mask an option to connect a first input and a second input to a first output and a second output in a straight configuration or a cross configuration, wherein said first input is coupled to said first output and said second input is coupled to said second output in said straight configuration, said first input being coupled to said second output and said second input being coupled to said first output in a cross configuration,
• wherein one of two logical values is provided on one of said first input and said second input, and another one of the two logical values is provided on the another one of said first input and said second input,
• wherein said first value is changed to said second value by changing configuration from cross to straight or straight to cross.

A method of allowing the value of a bit stored in integrated circuits to be changed when the design of integrated circuits changes, said method comprising:

• providing a register bit cell containing two inputs, wherein said register bit cell generates one logical value when said two inputs are in a connected status and another logical value when said two inputs are in a disconnected status;
• and
• providing a cell containing a plurality of fingers, each of said plurality of fingers containing space for a plurality of layers, wherein each of said plurality of layers is to be laid by a corresponding one of a plurality of masks using which said value of said bit is sought to be controlled, wherein whether said plurality of layers are laid or not determines whether said two inputs are in said connected status or said disconnected status.

An integrated circuit generating a desired bit value, said integrated circuit comprising:

• a register bit cell containing two inputs, wherein said register bit cell generates one logical value when said two inputs are in a connected status and another logical value when said two inputs are in a disconnected status;
• and
• a cell containing a plurality of fingers, each of said plurality of fingers containing space for a plurality of layers, wherein each of said plurality of layers is laid by a corresponding one of a plurality of masks using which said value of said bit is sought to be controlled, wherein whether said plurality of layers are laid or not determines whether said two inputs are in said connected status or said disconnected status.