Method and apparatus for allocating decoupling capacitor cells

An apparatus for allocating decoupling capacitor cells in an integrated circuit (IC) design, said apparatus comprising:

• means for obtaining geometrical information of rectangular areas in the IC design, each of the rectangular areas not intersecting any design figure in selected metal layers of the IC design in a design area;
• means for determining possible locations for rows of decoupling capacitor cell arrays to be placed in the rectangular areas, a row including a set of cell arrays to be placed across the rectangular areas in a direction of a first coordinate axis of the design area;
• means for determining for each possible location a number of decoupling capacitor cells included in the row;
• and
• means for selecting row locations satisfying a certain design rule from among the possible locations in a descending order of the number of the decoupling capacitor cells.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for allocating decoupling capacitor cells in an integrated circuit (IC) design, said method comprising:

• obtaining geometrical information of rectangular areas in the IC design, each of the rectangular areas not intersecting any design figure in a metal layer of the IC design in a design area;
• determining possible locations for rows of decoupling capacitor cell arrays to be placed in the rectangular areas, a row including a set of cell arrays to be placed across the rectangular areas in a direction of a first coordinate axis of the design area;
• determining for each possible location a number of decoupling capacitor cells included in the row;
• and
• selecting row locations satisfying a certain design rule from among the possible locations in a descending order of the number of the decoupling capacitor cells.