Pure fill via area extraction in a multi-wide object class design layout

A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, said design layout having multiple wide class objects on the first layer, said method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• sizing the w0 objects inward by an associated via enclosure rule w0 overVx to generate pure fill via areas (PFVA) for the w0 objects (w0 PFVA);
• representing the w0 PFVA as a current pure fill via area (CPFVA);
• for each successive wide class of objects i=1, n corresponding to geometries on the first layer:
• deriving the next higher numbered wide class object set wi corresponding to geometries on the first layer;
• eliminating portions of the CPFVA lying inside the wl objects and lying within a distance equal to an associated via enclosure rule wi overVx of any non-virtual boundary of the wi objects, to thereby form a resultant CPFVA valid for up to wi objects (wi CPFVA);
• representing the wn CPFVA as the PFVA for the first layer;
• and
• using the PFVA for the first layer to indicate where vias may be placed.

A method of processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout having multiple wide class objects on a first layer, said method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• sizing the w0 objects inward by an associated via enclosure rule w0 overVx to generate pure fill via areas (PFVA) for the w0 objects (w0 PFVA);
• representing the w0 PFVA as a current pure fill via area (CPFVA);
• for each successive wide class of objects i=1, n corresponding to geometries on the first layer:
• deriving the next higher numbered wide class object set wi corresponding to geometries on the first layer;
• eliminating portions of the CPFVA lying inside the wi objects and lying within a distance equal to an associated via enclosure rule wi overVx of any non-virtual boundary of the wl objects, to thereby form a resultant CPFVA valid for up to wl objects (wi CPFVA);
• representing the wn CPFVA as the PFVA for the first layer.

An electronic circuit fabricated from a design layout representation thereof, said design layout being generated by the steps of:

• representing geometries on the first layer by a w0 set of objects;
• sizing the w0 objects inward by an associated via enclosure rule w0 overVx to generate pure fill via areas (PFVA) for the w0 objects (w0 PFVA);
• representing the w0 PFVA as a current pure fill via area (CPFVA);
• for each successive wide class of objects i=1, n corresponding to geometries on the first layer:
• deriving the next higher numbered wide class object set wi corresponding to geometries on the first layer;
• eliminating portions of the CPFVA lying inside the wl objects and lying within a distance equal to an associated via enclosure rule wi overVx of any non-virtual boundary of the wl objects, to thereby form a resultant CPFVA valid for up to wl objects (wi CPFVA);
• representing the wn CPFVA as the PFVA for the first layer;
• and
• using the PFVA for the first layer to indicate where vias may be placed.

A computer readable encoding of an electronic circuit design, the computer readable encoding comprising:

• one or more design file media encoding representations of a multiple wide object class design layout having geometries on a first layer;
• wherein the computer readable encoding of the electronic circuit design was generated by the steps of:
• representing geometries on the first layer by a w0 set of objects;
• sizing the w0 objects inward by an associated via enclosure rule w0 overVx to generate pure fill via areas (PFVA) for the w0 objects (w0 PFVA);
• representing the w0 PFVA as a current pure fill via area (CPFVA);
• for each successive wide class of objects i=1, n corresponding to geometries on the first layer:
• deriving the next higher numbered wide class object set wi corresponding to geometries on the first layer;
• eliminating portions of the CPFVA lying inside the wl objects and lying within a distance equal to an associated via enclosure rule wl overVx of any non-virtual boundary of the wl objects, to thereby form a resultant CPFVA valid for up to wi objects (wl CPFVA);
• representing the wn CPFVA as the PFVA for the first layer.

An apparatus for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, said apparatus comprising:

• means for representing geometries on the first layer by a w0 set of objects;
• means for sizing the w0 objects inward by an associated via enclosure rule w0 overVx to generate pure fill via areas (PFVA) for the w0 objects (w0 PFVA);
• means for representing the w0 PFVA as a current pure fill via area (CPFVA);
• means for deriving the next higher numbered wide class object set wi corresponding to geometries on the first layer;
• for each successive wide class of objects i=1, n corresponding to geometries on the first layer:
• means for eliminating portions of the CPFVA lying inside the wi objects and lying within a distance equal to an associated via enclosure rule wl overVx of any non-virtual boundary of the wl objects, to thereby form a resultant CPFVA valid for up to wi objects (wl CPFVA);
• and
• means for representing the wn CPFVA as the PFVA for the first layer.

A computer readable encoding of instructions for a computer, said instructions encoding a method for use with a design layout, said encoded method for deriving one or more pure fill via areas (PFVA) for geometries on a first layer in a design layout having multiple wide class objects on the first layer, said encoded method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• sizing the w0 objects inward by an associated via enclosure rule w0 overVx to generate a PFVA for the w0 objects (w0 PFVA);
• representing the w0 PFVA as a current pure fill via area (CPFVA);
• for each successive wide class of objects i=1, n corresponding to geometries on the first layer:
• deriving the next higher numbered wide class object set wi corresponding to geometries on the first layer;
• eliminating portions of the CPFVA lying inside the wi objects and lying within a distance equal to an associated via enclosure rule wi overVx of any non-virtual boundary of the wl objects, to thereby form a resultant CPFVA valid for up to wi objects (wl CPFVA);
• representing the wn CPFVA as the PFVA for the first layer.