Via enclosure rule check in a multi-wide object class design layout
AssigneeSun Microsystems, Inc.
InventorsMu-Jing Li, Amy Yang
Life of this patent
Estimating the term…
Abstract
In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries of a wide class object, and not against the virtual boundaries. An exemplary embodiment provides a method for identifying as a violation, for each wide class wi object, any geometry on another layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object. The exemplary method is preferably performed using effective wide class objects.
Claims39
A method for use with a design layout, said method for checking geometries on a first layer for enclosure of geometries on a second layer, said method comprising the steps of:
- deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- for each wide class wi object, identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object.
A method for checking geometries on a first layer for enclosure of geometries on a second layer in a design layout, said method comprising the steps of:
- deriving wide class object sets w1, w2, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl1, encl2, encli, . . . , encln;
- for each wide class wi object:
- identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object.
A method for checking geometries on a first layer for enclosure of geometries on a second layer in a design layout, said method comprising the steps of:
- representing geometries on the first layer by a w0 set of objects;
- deriving wide class object sets w1, w2, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl1, encl2, encli, . . . , encln;
- for each wide class wi object:
- identifying as a violation any geometry on the second layer which overlaps a violation region of each wi object, said violation region extending inward from non-virtual edges and from the end-most encli portions of virtual edges of each wi object, said violation region extending inward by an amount equal to the respective enclosure rule encli for the wide class wi.
A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, said design layout having geometries on a first layer which enclosure geometries on a second layer, said method comprising the steps of:
- deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- for each wide class wi object, identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object;
- and
- correcting any identified violations.
A method of processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout having geometries on a first layer which enclosure geometries on a second layer, said method comprising the steps of:
- deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- for each wide class wi object, identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object;
- and correcting any identified violations.
An electronic circuit fabricated from a design layout representation thereof having geometries on a first layer which enclosure geometries on a second layer, said design layout being generated by the steps of:
- deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- for each wide class wi object, identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object;
- and
- correcting any identified violations.
A computer readable encoding of an electronic circuit design, the computer readable encoding comprising:
- one or more design file media encoding representations of geometries on a first layer which enclosure geometries on a second layer;
- wherein the computer readable encoding of the electronic circuit design was generated by the steps of:
- deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- for each wide class wi object, identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object;
- and
- correcting any identified violations.
An apparatus for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, said design layout having geometries on a first layer which enclosure geometries on a second layer, said apparatus comprising:
- means for deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- means for identifying as a violation, for each wide class wi object, any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object.
A computer readable encoding of instructions for a computer, said instructions encoding a method for use with a design layout, said method for checking geometries on a first layer for enclosure of geometries on a second layer, said encoded method comprising the steps of:
- deriving wide class object sets w0, w1, w2, wi, . . . wn corresponding to geometries on the first layer, each having a respective enclosure rule encl0, encl1, encl2, encli, . . . , encln;
- for each wide class wi object, identifying as a violation any geometry on the second layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object.
Dependencies are inferred from the claim text.