Method and apparatus for improving reliability in computer processors by re-executing instructions
OwnerSudarshan Kadambiinventor
Life of this patent
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Abstract
One embodiment of the present invention provides a system that improves reliability in a compute processor by re-executing instructions. During operation, the system issues an instruction to an execution unit within the computer processor. The execution unit subsequently executes the instruction to produce a first result. If an idle execution slot becomes available, the system reissues the instruction to the execution unit, which causes the instruction to be executed a second time to produce a second result. The system then compares the first result with the second result. If the first result is not identical to the second result, the system flags an error.
Claims20
A method that verifies results produced during execution of computer instructions, comprising:
- issuing an instruction to an execution unit;
- executing the instruction in the execution unit to produce a first result;
- and
- if an idle execution slot is available,
- reissuing the instruction to the execution unit,
- executing the instruction a second time to produce a second result,
- comparing the first result with the second result, and
- if the first result is not identical to the second result, flagging an error.
An apparatus that verifies results produced during execution of computer instructions, comprising:
- an issuing mechanism that is configured to issue an instruction to an execution unit;
- an instruction execution unit that is configured to execute the instruction to provide a first result;
- a determining mechanism that is configured to determine if an idle execution slot is available;
- a reissuing mechanism that is configured to reissue the instruction to the execution unit;
- wherein the instruction execution unit is further configured to re-execute the instruction to provide a second result;
- a comparing mechanism that is configured to compare the first result with the second result;
- and
- a flagging mechanism that is configured to flag an error if the first result is not identical to the second result.
A computer processor that executes a method that verifies results produced during execution of computer instructions, the method comprising:
- issuing an instruction to an execution unit;
- executing the instruction in the execution unit to produce a first result;
- and
- if an idle execution slot is available,
- reissuing the instruction to the execution unit,
- executing the instruction a second time to produce a second result,
- comparing the first result with the second result, and
- if the first result is not identical to the second result, flagging an error.
A computer system including a processor that executes a method that verifies results produced during execution of computer instructions, the method comprising:
- issuing an instruction to an execution unit;
- executing the instruction in the execution unit to produce a first result;
- and
- if an idle execution slot is available,
- reissuing the instruction to the execution unit,
- executing the instruction a second time to produce a second result,
- comparing the first result with the second result, and if the first result is not identical to the second result, flagging an error.
Dependencies are inferred from the claim text.